Journal of the Institute of Electronics Engineers of Korea SD (대한전자공학회논문지SD)

The Institute of Electronics and Information Engineers (대한전자공학회)
권호 표지

Reviews and Proposals of Low-Voltage DRAM Circuit Design

저전압 DRAM 회로 설계 검토 및 제안

  • 김영희 (창원대학교 전자공학과) ;
  • 김광현 (포항공과대학교 전자전기공학과) ;
  • 박홍준 (포항공과대학교 전자전기공학과) ;
  • 위재경 (현대전자 메모리개발연구소) ;
  • 최진혁 (현대전자 메모리개발연구소)
  • Published : 2001.04.01
Download PDF
⟨ Previous Next ⟩

Abstract

As the device scaling proceeds, the operating voltage(VDD) of giga-bit DRAMs is expected to be reduced to 1.5V or down, fir improving the device reliability and reducing the power dissipation. Therefore the low-voltage circuit design techniques are required to implement giga-bit DRAMs. In this work, state-of-art low-voltage DRAM circuit techniques are reviewed, and four kinds of low-voltage circuit design techniques are newly proposed for giga-bit DRAMs. Measurement results of test chips and SPICE simulation results are presented for the newly proposed circuit design techniques, which include a hierarchical negative-voltage word-line driver with reduced subthreshold leakage current, a two-phase VBB(Back-Bias Voltage) generator, a two-phase VPP(Boosted Voltage) generator and a bandgap reference voltage generator.

반도체 소자가 소형화 되면서 소자의 신뢰성을 유지하고 전력 소모를 줄이기 위해 기가-비트 DRAM의 동작 전압은 1.5V 이하로 줄어들 것으로 기대된다. 따라서 기가-비트 DRAM을 구현하기 위해 저전압 회로 설계 기술이 요구된다. 이 연구에서는 지금까지 발표된 저전압 DRAM 회로 설계 기술에 대한 조사결과를 기술하였고, 기가-비트 DRAM을 위해 4가지 종류의 저전압 회로 설계 기술을 새로이 제안하였다. 이 4가지 저전압 회로 설계 기술은 subthreshold 누설 전류를 줄이는 계층적 negative-voltage word-line 구동기, two-phase VBB(Back-Bias Voltage) 발생기, two-phase VPP(Boosted Voltage) 발생기와 밴드갭 기준전압 발생기에 대한 것인데, 이에 대한 테스트 칩의 측정 결과와 SPICE 시뮬레이션 결과를 제시하였다.

Keywords

References

  1. Y.Nagagome et al., 'An Experimental 1.5-V 64-Mb DRAM,' IEEE. J. Solid-State Circuits, vol. 26, pp. 465-472, April 1991 https://doi.org/10.1109/4.75040
  2. Y.Nakagome et al., 'Reviews and Prospects of DRAM Technology,' IEICE Transactions, vol. E74, pp. 799-811, April 1991
  3. T.Yamagata et al., 'Low Voltage Circuit Design Techniques for Battery-Operated and/or Giga-Scale DRAM's,' IEEE. J. Solid-State Circuits, vol. 30, pp. 1183-1188, Nov. 1995 https://doi.org/10.1109/4.475705
  4. M.Asakura et al., 'An Experimental 256-Mb DRAM with Boosted Sense-Ground Scheme,' IEEE. J. Solid-State Circuits, vol. 29, pp. 1303-1309, Nov. 1994 https://doi.org/10.1109/4.328628
  5. M.Nakamura et al., 'A 29-ns 64-Mb DRAM with Hierarchical Array Architecture,' IEEE. J. Solid-State Circuits, vol. 31, pp. 1302-1306, Sep. 1996 https://doi.org/10.1109/4.535414
  6. T.Kawahara et al., 'Subthreshold Current Reduction for Decoded-Driver by Self-Reverse Biasing,' IEEE. J. Solid-State Circuits, vol. 28, pp. 1136-1144, Nov. 1993 https://doi.org/10.1109/4.245594
  7. T.Sakata et al., 'SUBTHRESHOLD-CURRENT REDUCTION CIRCUITS FOR MULTI-GIGABIT DRAM'S,' Symp. VLSI Tech-nology, Dig. Tech. Papers, pp. 45-46, May 1993
  8. T.Kawahara et al., 'A Circuit Technology for Sub-10ns ECL 4Mb BiCMOS DRAMs,' in Symp. VLSI Technology, Dig. Tech. Papers, pp. 131-132, May 1991
  9. S.Fujii et al., 'A 45-ns 16-Mbit DRAM with Triple-Well Structure,' IEEE. J. Solid-State Circuits, vol. 24, pp. 1170-1175, Oct. 1989 https://doi.org/10.1109/JSSC.1989.572574
  10. A.Hatakeyama et al., 'A 256-Mb SDRAM Using a Register-Controlled Digital DLL,' IEEE. J. Solid-State Circuits, vol. 32, pp. 1728-1734, Nov. 1997 https://doi.org/10.1109/4.641693
  11. T.Ooishi et al., 'A Well-Synchronized Sensing/Equalizing Method for Sub-1.0-V Operating Advanced DRAM's,' IEEE. J. Solid-State Circuits, vol. 29, pp. 432-440, April 1994 https://doi.org/10.1109/4.280692
  12. Y.H.Kim et al., 'Analysis and Prevention of DRAM Latch-Up During Power-On,' IEEE. J. Solid-State Circuits, vol. 32, pp. 79-85, Jan. 1997 https://doi.org/10.1109/4.553181
  13. Y.Tsukikawa et al., 'An Efficient Back-Bias Generator with Hybrid Pumping Circuit for 1.5-V DRAMs,' IEEE. J. Solid-State Circuits, vol. 29, pp. 534-538, April 1994 https://doi.org/10.1109/4.280705
  14. Y.H.Kim et al., 'Two-Phase Back-Bias Voltage Generator for Low-Voltage Gigabit DRAMs,' IEE Electronics Letters, vol.34, pp. 1831-1833, Sept. 1998 https://doi.org/10.1049/el:19981332
  15. P.Favrat et al., 'A High-Efficiency CMOS Voltage Doubler,' IEEE. J. Solid-State Circuits, vol. 33, pp. 410-416, March 1998 https://doi.org/10.1109/4.661206
  16. Y.H.Kim et al., 'Two-Phase Boosted Voltage Generator for Low-Voltage Giga-bit DRAMs,' IEICE Transactions on Electron., vol.E83-C, pp. 266-269, Feb. 2000
  17. Y.H.Kim et al., 'Fully On-Chip Current Controlled Open-Drain Output Driver for High-Bandwidth DRAMs,' IEICE Transactions on Electron., vol.E82-C, pp. 2101-2104, Nov. 1999
  18. M.Horiguchi et al., 'A Tunable CMOS DRAM Voltage Limiter with Stabilized Feedback Amplifier,' IEEE. J. Solid-State Circuits, vol. 25, pp. 1129-1135, Oct. 1990 https://doi.org/10.1109/4.62133
  19. H.Banba et al., 'A CMOS Bandgap Reference Circuit with Sub-1V Operation,' IEEE. J. Solid-State Circuits, vol. 34, pp. 670-674, May 1999 https://doi.org/10.1109/4.760378
  20. Y.H.Kim et al., 'A Temperature-and Supply-Insensitive Fully On-Chip 1Gb/s CMOS Open-Drain Output Driver for High-Bandwidth DRAMs,' submitted for possible publication in the IEEE. J. Solid-State Circuits, May 2000