Journal of the Institute of Electronics Engineers of Korea SD (대한전자공학회논문지SD)

The Institute of Electronics and Information Engineers (대한전자공학회)
권호 표지

Fault Coverage Metric for Delay Fault Testing

지연 고장 테스팅에 대한 고장 검출율 메트릭

  • 김명균 ((주) 코아로직 연구원) ;
  • 강성호 (연세대학교 전기·전자공학과) ;
  • 한창호 (인하대학교 전자전기컴퓨터공학부) ;
  • 민형복 (성균관대학교 전자전기컴퓨터공학부)
  • Published : 2001.04.01
Download PDF
⟨ Previous Next ⟩

Abstract

Due to the rapid development of semiconductor technology, the complexity of VLSI circuits has heavily increased. With the increased densities of integrated circuits, several different types of faults can occur Thus, testing such circuits is becoming a sever problem. Delay testing can detect system timing failures caused by delay faults. However, the conventional delay fault coverage in terms of the number of detected faults may not be an effective measure of delay testing because, unlike a stuck-at-faults, the impact of a delay fault is dependent on its delay defect size rather than on its existence. Thus, the effectiveness of delay testing is dependent on the propagation delay of the path to be tested, the delay defect size, and the system clock interval. This paper proposes a new delay defect fault coverage that considers both propagation delay of the path to be tested and additional delay defect size. And the relationship between delay defect fault coverage and defect level is analyzed.

빠른 반도체 기술의 발전으로 인하여 VLSI 회로의 복잡도는 크게 증가하고 있다. 그래서 복잡한 회로를 테스팅하는 것은 아주 어려운 문제로 대두되고 있다. 또한 집적회로의 증가된 집적도로 인하여 여러 가지 형태의 고장이 발생하게 됨으로써 테스팅은 더욱 중요한 문제로 대두되고 있다. 이제까지 일반적으로 지연 고장 테스팅에 대한 신뢰도는 가정된 고장의 개수에 대한 검출된 고장의 개수로 표현되는 전통적인 고장 검출율로서 평가되었다. 그러나 기존의 교장 검출율은 고장 존재의 유무만을 고려한 것으로써 실제의 지연 고장 테스팅에 대한 신뢰도와는 거리가 있다. 지연 고장 테스팅은 고착 고장과는 달리 경로의 진행 지연과 지연 결함 크기 그리고 시스템 동작 클럭 주기에 의존하기 때문이다. 본 논문은 테스트 중인 경로의 진행 지연과 지연 결함 크기를 고려한 새로운 고장 검출율 메트릭으로서지연 결함 고장 검출율(delay defect fault coverage)을 제안하였으며, 지연 결함 고장 검출율과 결함 수준(defect level)과의 관계를 분석하였다.

Keywords

References

  1. V. Iyengar, B. Rosen, and I. Spillinger, 'Delay Test Generation Algebra and Algorithms,' Proc. of International Test Conference, pp. 867-876, 1988 https://doi.org/10.1109/TEST.1988.207874
  2. Van, Brakel, G. et al., 'Gate Delay Fault Test Generation for Non-Scan Circuits,' Proc. of International Test Conference, pp. 308-312, 1995 https://doi.org/10.1109/EDTC.1995.470379
  3. K-T. Cheng and S. Devadas and K. Keutzer, 'Delay-Fault Test Generation and Synthesis for Testability under a Standard Design Methodology,' IEEE Trans. on CAD, Aug. 1993, pp.1217-1231 https://doi.org/10.1109/43.238614
  4. J. Waicukauski, E. Lindbloom, B. Rosen and V. lyengar, 'Transition Fault Simulation,' IEEE Design and Test, pp. 32-38, April 1987 https://doi.org/10.1109/MDT.1987.295104
  5. S. Reddy, C. Lin and Patil, 'An Automatic Test Pattern Generation for the Detection of Path Delay Fault,' Proc. ICCAD, pp. 284-287, 1987
  6. Smith, G. L., 'Model for Delay Faults Based upon Path,' Proc. of International Test Conference, pp. 342-349, 1985
  7. D. M. Wu, C. E. Radke, and J. P. Roth, 'Statistical AC Test Coverage,' Proc. of International Test Conference, pp. 538-541, 1986
  8. J. L. Cater, V. S. Iyengar, and B. K. Rosen, 'Efficient Test Coverage Determination for Delay Faults,' Proc. of International Test Conference, pp. 418-428, 1987
  9. S. Tragoudas, 'Accurate Path Delay Fault Coverage is Feasible,' Proc. of International Test Conference, pp. 201-210, 1999 https://doi.org/10.1109/TEST.1999.805631
  10. T. W. Williams, and N. C. Brown, 'Defect Level as a Function of Fault Coverage,' IEEE Trans, on Computer, Vol. C-32, No. 12, pp. 987-988, 1981 https://doi.org/10.1109/TC.1981.1675742
  11. F. Coris, S. Martino, and T. W. Williams, 'Defect Level as a Function of Fault Coverage and Yield,' Proc. of European Test Conference(ETC), pp. 507-508, 1993 https://doi.org/10.1109/ETC.1993.246604
  12. Eun Sei Park, M.R. Mercer, T.W. Williams, 'A Statistical Model for Delay-Fault Testing', IEEE Design & Test of Computer, pp. 45-55, February, 1989 https://doi.org/10.1109/54.20389
  13. James, H. Shelly and David, R. Trayon, 'Statistical Techniques of Testing Verification,' Proc. 20th Design Automation Conference, pp. 396-402, 1983
  14. Mustapha Hamad, Sami Al-Arian and David Landis, 'A Statical Methodology for Modeling and Analysis of Path Delay Faults in VLSI Circuits,' Computer and Electrical Eng. Vol. 23, No. 5, pp. 319-328, 1997 https://doi.org/10.1016/S0045-7906(97)00017-7
  15. Nandakumar N. Tendolkar, 'Analysis of Timing Failure Due to Random AC Defects in VLSI Circuits,' Proc. 22nd Design Automation Conference, pp. 709-714, 1985
  16. Jacques Benkoski and Andrzej J. Strojwas, 'Computation of Delay Defect and Delay Fault Probabilities Using a Statistical Timing Simulator,' Proc. of International Test Conference, pp. 153-160, 1989 https://doi.org/10.1109/TEST.1989.82289
  17. Alberto Leon-Garcia, Random Processes for Electrical Engineering, Second Edition, Addison Wesley