JSTS:Journal of Semiconductor Technology and Science

The Institute of Electronics and Information Engineers (대한전자공학회)
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High Performance p-type SnO thin-film Transistor with SiOx Gate Insulator Deposited by Low-Temperature PECVD Method

  • U, Myeonghun (School of Electrical and Electronics Engineering, Chung-Ang University) ;
  • Han, Young-Joon (School of Electrical and Electronics Engineering, Chung-Ang University) ;
  • Song, Sang-Hun (School of Electrical and Electronics Engineering, Chung-Ang University) ;
  • Cho, In-Tak (Department of Electrical and Computer Engineering, Seoul National University) ;
  • Lee, Jong-Ho (Department of Electrical and Computer Engineering, Seoul National University) ;
  • Kwon, Hyuck-In (School of Electrical and Electronics Engineering, Chung-Ang University)
  • Received : 2014.06.12
  • Accepted : 2014.08.11
  • Published : 2014.10.30
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Abstract

We have investigated the gate insulator effects on the electrical performance of p-type tin monoxide (SnO) thin-film transistors (TFTs). Various SnO TFTs are fabricated with different gate insulators of a thermal $SiO_2$, a plasma-enhanced chemical vapor deposition (PECVD) $SiO_x$, a $150^{\circ}C$-deposited PEVCD $SiO_x$, and a $300^{\circ}C$-deposited PECVD $SiO_x$. Among the devices, the one with the $150^{\circ}C$-deposited PEVCD $SiO_x$ exhibits the best electrical performance including a high field-effect mobility ($=4.86cm^2/Vs$), a small subthreshold swing (=0.7 V/decade), and a turn-on voltage around 0 (V). Based on the X-ray diffraction data and the localized-trap-states model, the reduced carrier concentration and the increased carrier mobility due to the small grain size of the SnO thin-film are considered as possible mechanisms, resulting in its high electrical performance.

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References

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