• The Transactions of the Korean Institute of Electrical Engineers C
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• v.49 no.1
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• pp.59-63
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• 2000

For the Mo-tip field emitter array, the method by which the geometrical structure of the gate insulator wall could be modified in order to improve field emission properties(turn-on voltage and gate leakage current). The device having a gate insulator of complex shape, which means the combined geometrical structure with round shape made by wet etching and vertical shape made by dry etching processes, was fabricated and the field emission properties of the three kinds of devices were compared. As a result, the electric field applied to tip apex could be increased and gate leakage current could be decreased by employing the gate insulator having geometrical wall structure of mixed shape. Finally, the obtained empirical results were analyzed by simulation of electric field distribution at/near the tip apex and gate insulator using SNU-FEAT simulator.

• Proceedings of the KIEE Conference
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• 1999.07d
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• pp.1965-1967
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• 1999

We have investigated the electrical characteristics of the poly-Si TFT's with the novel gate insulator structure. The gate insulator makes the offset region to reduce leakage current, and the electrical characteristics are obtained by employing Virtual Wafer Fab. simulator. As increases the gate insulator thickness above the offset region of this structure from $0{\AA}$ to $2000{\AA}$, the OFF state current at $V_G$=10V decrease by two orders in magnitude while ON state current doesn't decrease significantly. ON/OFF current ratios for conventional device and the proposed device with $2000{\AA}$ gate insulator thickness are $1.68{\times}10^5$ and $1.07{\times}10^7$, respectively.

• JSTS:Journal of Semiconductor Technology and Science
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• v.10 no.1
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• pp.66-77
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• 2010

Improvement in breakdown voltage ($BV_{ds}$) and speed of the device are the key issues among the researchers for enhancing the performance of HEMT. Increased speed of the device aspires for shortened gate length ($L_g$), but due to lithographic limitation, shortening $L_g$ below sub-micrometer requires the inclusion of various metal-insulator geometries like T-gate onto the conventional architecture. It has been observed that the speed of the device can be enhanced by minimizing the effect of upper gate electrode on device characteristics, whereas increase in the $BV_{ds}$ of the device can be achieved by considering the finite effect of the upper gate electrode. Further, improvement in $BV_{ds}$ can be obtained by applying field plates, especially at the drain side. The important parameters affecting $BV_{ds}$ and cut-off frequency ($f_T$) of the device are the length, thickness, position and shape of metal-insulator geometry. In this context, intensive simulation work with analytical analysis has been carried out to study the effect of variation in length, thickness and position of the insulator under the gate for various metal-insulator gate geometries like T-gate, $\Gamma$-gate, Step-gate etc., to anticipate superior device performance in conventional HEMT structure.

• 한국정보디스플레이학회:학술대회논문집
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• 2009.10a
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• pp.1422-1424
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• 2009

Modified self-assembled $TiO_2$ and polyelectrolyte multilayer film have been used as OTFT insulator. Both films were used as gate insulator and their thickness were reduced to the order of 10nm. The operating voltage of OTFT was substantially reduced due to nanoscale thickness of titanium oxide and polyelectrolyte multilayer. Pentacene-based OTFT characteristics will be discussed.

• JSTS:Journal of Semiconductor Technology and Science
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• v.9 no.3
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• pp.136-147
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• 2009

In this paper we analyze the influence of source/drain (S/D) extension region design for minimizing short channel effects (SCEs) in 25 nm gate length single and double gate Silicon-on-Insulator (SOI) and Germanium-on-Insulator (GOI) MOSFETs. A design methodology, by evaluatingm the ratio of the effective channel length to the natural length for the different devices (single or double gate FETs) and technology (SOI or GOI), is proposed to minimize short channel effects (SCEs). The optimization of non-overlapped gate-source/drain i.e. underlap channel architecture is extremely useful to limit the degradation in SCEs caused by the high permittivity channel materials like Germanium as compared to that exhibited in Silicon based devices. Subthreshold slope and Drain Induced Barrier Lowering results show that steeper S/D gradients along with wider spacer regions are needed to suppress SCEs in GOI single/double gate devices as compared to Silicon based MOSFETs. A design criterion is developed to evaluate the minimum spacer width associated with underlap channel design to limit SCEs in SOI/GOI MOSFETs.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2009.04a
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• pp.72-73
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• 2009

In this study, we fabricated of pentacene organic thin film trasistor(OTFT), which used aluminum oxide for the gate insulator on glass substrate. Aluminum oxide for OTFTs was deposited on the gate layer by E-beam evaporation. aluminum oxide fabricated various deposition rate. In this case of the deposition rate of $0.1\;{\AA}$, the fabricated aluminum oxide gate insulator OTFT showed a threshold voltage of -1.36V, an on/off current ratio of $1.9{\times}l0^3$ and field effect mobility $0.023\;cm^2/V_s$.

• Journal of Information Display
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• v.6 no.2
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• pp.16-18
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• 2005

Hybrid insulator pentacene thin film transistors (TFTs) are fabricated with thermally grown oxide and cross-linked polyvinylalcohol (PVA) including surface treatment by dilute ploymethylmethacrylate (PMMA) layer on $n^+$ doped silicon wafer. Through the optimization of $SiO_2$ layer thickness in hybrid insulator structure, carrier mobility is increased to more than 35 times than that of the TFT which has only a gate insulator of $SiO_2$ at the same electric field. The carrier mobility of $1.80cm^2$/V-s, subthreshold swing of 1.81 V/decade, and $I_{on}/I_{off}$ current ratio> $1.10{\times}10^5$ are obtained less than -30 V bias condition. The result is one of the best reported performances of pentacene TFTs with hybrid insulator including cross-linked PVA layer as a gate insulator at relatively low voltage operation.

• 한국정보디스플레이학회:학술대회논문집
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• 2002.08a
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• pp.184-187
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• 2002

In this work, the electrical characteristics of organic thin film transistors with the stacked organic gate insulators have been studied. PVP(Polyvinylphenol) and polystyrene were used as gate insulating materials. Both the high dielectric constant of PVP and better insulating capability of polystyrene were compensatorily adopted in two different stacking orders of PVP-polystyrene and polystyrene-PVP. The output characteristics of the device with the stacked gate insulator showed substantial improvement compared with those of the devices with either PVP or polystyrene gate insulator: Furthermore, these stacked organic gate insulators can differently affect the TFT characteristics with the stacking orders. The electrical properties of TFTs with organic gate insulators stacked in different orders are discussed.

• JSTS:Journal of Semiconductor Technology and Science
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• v.7 no.2
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• pp.120-131
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• 2007

A comprehensive short channel analytical model has been proposed for High Electron Mobility Transistor (HEMT) to obtain higher cut-off frequency maintaining the reliability of the device. The model has been proposed to consider generalized doping variation in the directions perpendicular to and along the channel. The effect of field plates and different gate-insulator geometry (T-gate, etc) have been considered by dividing the area between gate and the high band gap semiconductor into different regions along the channel having different insulator and metal combinations of different thicknesses and work function with the possibility that metal is in direct contact with the high band gap semiconductor. The variation obtained by gate-insulator geometry and field plates in the field and channel potential can be produced by varying doping concentration, metal work-function and gate-stack structures along the channel. The results so obtained for normal device structure have been compared with previous proposed model and numerical method (finite difference method) to prove the validity of the model.

• The Transactions of the Korean Institute of Electrical Engineers C
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• v.50 no.4
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• pp.161-168
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• 2001

Organic thin film transitors(TFTs) are of interest for use in broad area electronic applications. For example, in active matrix liquid crystal displays(AMLCDs), organic TFTs would allow the use of inexpensive, light-weight, flexible, and mechanically rugged plastic substrates as an alternative to the glass substrates needed for commonly used hydrogenated amorphous silicon(a-Si:H). Recently pentacene TFTs with carrier field effect, mobility as large as 2 $cm^2V^{-1}s^{-1}$ have been reported for TFTs fabricated on silicon substrates, and it is higher than that of a-Si:H. But these TFTs are fabricated on silicon wafer and $SiO_2$ was used as a gate insulator. $SiO_2$ deposition process requires a high insulator which is polyimide and photo acryl. We investigated trasfer and output characteristics of the thin film transistors having active layer of pentacene. We calculated field effect mobility and on/off ratio from transfer characteristics of pentacene thin film transistor, and measured IR absorption spectrum of polymide used as the gate dielectric layer. It was found that using the photo acryl as a gate insulator, threshold voltage decreased from -12.5 V to -7 V, field effect mobility increased from 0.012 $cm^2V^{-1}s^{-1}$ to 0.039 $cm^2V^{-1}s^{-1}$ , and on/off current ratio increased from $10^5\;to\;10^6$. It seems that TFTs using photo acryl gate insulator is apt to form channel than TFTs using polyimide gate insulator.