• Proceedings of the IEEK Conference
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• 2008.06a
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• pp.585-586
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• 2008

In this paper, a novel beta-multiplier reference current source circuit for the 800mV power-supply voltage is presented. In order to cope with the narrow input common-mode range of the OpAmp in the reference circuit, shunt resistive voltage divider branches were deployed. High gain OpAmp was designed to compensate intrinsic low output resistance of the MOS transistors. The proposed reference circuit was designed in a standard 0.18um CMOS process with nominal Vth of 420mV and -450mV for nMOS and pMOS transistor respectively. The total power consumption including OpAmp is less than 50uW.

• Proceedings of the IEEK Conference
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• 2002.07a
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• pp.646-649
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• 2002

In this paper, a low-voltage CMOS squarer and a four-quadrant analog multiplier are presented. It is based on a source-coupled pair and a scaled-floating voltage generator which are modified to work as a voltage squaring and a sum/difference circuits. The proposed squarer/multiplier have been simulated with HSPICE, where -3㏈ bandwidth of 10MHz is achieved. The power consumption is about 0.6㎽, from a ${\pm}$1.5V supply, and the total harmonic distortion is less than 0.7%, with a 1.2V peak-to-peak 1MHz input signal.

• Proceedings of the IEEK Conference
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• 2000.06b
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• pp.149-152
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• 2000

A dual-mode multiplier (DMM) that performs single- and double-precision multiplications has been designed. An algorithm for efficiently implementing double-precision multiplication with a single-precision multiplier was proposed, which is based on partitioning double-precision multiplication into four single-precision sub-multiplications and computing them with sequential accumulations. When compared with conventional double-precision multipliers, our approach reduces the hardware complexity by about one third resulting in small silicon area and low-power dissipation at the expense of increased latency and throughput cycles.

• Proceedings of the KIPE Conference
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• 2004.07a
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• pp.121-124
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• 2004

In this paper, Simple and inexpensive analog maximum power point tracker (MPPT) algorithm for photovoltaic power system and low power system of doesn't use digital signal processor (DSP). The control circuit is composed such that the actual current and voltage are sensed directly from the PV array. These two signals are then multiplied by a single-chip multiplier. The multiplier output go through different time constants genesis pulse width modulated to switch. Finally those were verified through simulation.

• Proceedings of the IEEK Conference
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• 2001.06e
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• pp.47-50
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• 2001

Nowadays ARM7 core is used in many fields such as PDA systems because of the low power and low cost. It is a general-purpose processor, designed for both efficient digital signal processing and controller operations. But the advent of the wireless communication creates a need for high computational performance for signal processing. And then This paper has been designed a floating-point multiplier compatible to IEEE-754 single precision format for ARMTTDMI performance improvement.

• Proceedings of the IEEK Conference
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• 2000.06b
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• pp.205-208
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• 2000

In this paper, a low voltage CMOS analog four-quadrant multiplier using two V-I converters is presented. The proposed V-I converter is composed of the series composite transistor and the low voltage composite transistor. The designed analog four-quadrant multiplier has simulated by HSPICE using 0.25$\mu\textrm{m}$ n-well CMOS process parameters with a 2V supply voltage. Simulation results show that the power dissipation is 1.55㎿, the cutoff frequency is 489MHz, and the THD can be 0.26％ at maximum differential input of 1V$\sub$p-p/.

• Journal of Electrical Engineering and Technology
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• v.6 no.6
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• pp.817-823
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• 2011

This paper introduces an efficient voltage multiplier circuit for improved voltage gain and power efficiency of radio frequency identification (RFID) tags. The multiplier is fully integratable and takes advantage of both passive and active circuits to reduce the required input power while yielding the desired DC voltage. A six-stage voltage multiplier and an ultralow power voltage regulator are designed in a 0.13 ${\mu}m$ complementary metal-oxide semiconductor process for 2.45 GHz RFID applications. The minimum required input power for a 1.2 V supply voltage in the case of a 50 ${\Omega}$ antenna is -20.45 dBm. The efficiency is 15.95% for a 1 $M{\Omega}$ load. The regulator consumes 129 nW DC power and maintains the reference voltage in a 1.1% range with $V_{dd}$ varying from 0.8 to 2 V. The power supply noise rejection of the regulator is 42 dB near a 2.45 GHz frequency and performs better than -32 dB from 100 Hz to 10 GHz frequencies.

• Proceedings of the IEEK Conference
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• 2001.06b
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• pp.377-380
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• 2001

In this paper, we propose new partial product compressor and ENMODL (Enhanced-NORA-MODL) CLA(Carry Look-ahead Adder) for high speed and low power multiplier. To reduce transistor count, area, power we developed two new-approaches. One is small size partial product compressor, the other is dynamic CMOS logic ENMODL CLA. The transistor count of new compressor is reduced by 11% as compared with that of conventional one. The speed of ENMODL CLA is increased by 6.27% as compared with NMODL CLA.

• Journal of Korea Society of Industrial Information Systems
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• v.18 no.5
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• pp.9-14
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• 2013

This paper is designed frequency multiplier with low phase noise using DLL technique. The VCDL is designed using a differential structure to reduce common-mode noise. The proposed frequency multiplier is fabricated in a 65nm, 1.2V TSMC CMOS process, and the operating frequency range from 10MHz to 24MHz was measured. The SSB phase noise is measured to be -125dBc/Hz at 1MHz from 38.4MHz carrier. A total area of $0.032mm^2$were consumed in the chip, including the output buffer. Total current is 1.8mA at 1.2V supply voltage.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2001.10a
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• pp.617-620
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• 2001

This paper describes an efficient error-compensation technique for designing a low-error truncated Booth multiplier that receives two N-bit numbers and produces an N-bit product by eliminating the N least-significant bits. Applying the proposed method, a truncated Booth multiplier for area-efficient and low-power applications has been designed, and its performance (truncation error, area) was analyzed. Since the truncated Booth multiplier omits about half the partial product generators and adders, it has an area reduction by about 35%~40%, compared with non-truncated parallel multipliers. Error analysis shows that the proposed approach reduces the average truncation error by approximately 30%~40%, compared with conventional methods.