• Journal of the Korean Vacuum Society
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• v.19 no.2
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• pp.114-120
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• 2010

Conventional surface texturing in crystalline silicon solar cell have been use wet texturing by Alkali or Acid solution. But conventional wet texturing has the serious issue of wafer breakage by large consumption of wafer in wet solution and can not obtain the reflectance below 10% in multi crystalline silicon. Therefore it is focusing on RIE texturing, one method of dry etching. We developed large scale plasma RIE (Reactive Ion Etching) equipment which can accommodate 144 wafers (125 mm) in tray in order to provide surface texturing on the silicon wafer surface. Reflectance was controllable from 3% to 20% in crystalline silicon depending on the texture shape and height. We have achieved excellent reflectance below 4% on the weighted average (300~1,100 nm) in multi crystalline silicon using plasma texturing with gas mixture ratio such as $SF_6$, $Cl_2$, and $O_2$. The texture shape and height on the silicon wafer surface have an effect on gas chemistry, etching time, RF frequency, and so on. Excellent conversion efficiency of 16.1% is obtained in multi crystalline silicon by RIE process. In order to know the influence of RF frequency with 2 MHz and 13.56 MHz, texturing shape and conversion efficiency are compared and discussed mutually using RIE technology.

• Proceedings of the KIEE Conference
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• 1994.07b
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• pp.1463-1465
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• 1994

The electrical characteristics of $Al/Ta_2O_5/Si$ metal-oxide-semiconductor (MOS) capacitors were studied. $Ta_2O_5$ films on p-type silicon had been prepared by ionized cluster beam epitaxy technique (ICBE). This $Ta_2O_5$ films have low leakage current, high breakdown strength and low flat band shift. In this research, a single crystalline cpitaxial film of $Ta_2O_5$ has been grown on p-Si wafer using an ICBE technique. The native oxide layer ($SiO_2$) on the silicon substrate was removed below $500^{\circ}C$ by use of an accelerated arsenic ion beam, instead of a high temperature deposition. $Ta_2O_5$ films formed by ICBE technique can be received considerable attention for applications to coupling capacitors, gate dielectrics in MOS devices, and memory storage capacitor insulator because of their high dielectric constants above 20 and low temperature process.

• Transactions on Electrical and Electronic Materials
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• v.2 no.2
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• pp.32-36
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• 2001

A new solid source for low temperature diffusion into silicon was developed. The source wafer consists of an “active” compound, which is sol-gel prepared phosphosilicate glass-ceramics containing 56% P$_2$O$\sub$5/, embedded in a skeletal foam-like, inert substrate. Phosphorus diffusion from the new solid sources at low temperatures (800-875$^{\circ}C$) produced reprodecible sheet resistances and shallow junctions. From a series of one hour doping runs, the life time of the phosphosilicate source was determined to be over 40 hours. The effective diffusion coefficient of phosphorus into silicon and the corresponding activation energy at 850$^{\circ}C$ were determined to be 7.5${\times}$10$\^$-15/ $\textrm{cm}^2$/sec and ∼3.9 eV, respectively.

• Korean Journal of Materials Research
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• v.18 no.6
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• pp.307-312
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• 2008

In this study, a new cleaning process with a low cost of ownership (CoO) was developed with ozonated DI water ($DIO_3$). An ozone concentration of 40 ppm at room temperature was used to remove organic wax film and particles. Wax residues thicker than $200\;{\AA}$ remained after only a commercial dewaxer treatment. A $DIO_3$ treatment in place of a dewaxer showed a low removal rate on a thick wax layer of $8000\;{\AA}$ due to the diffusion-limited reaction of ozone. A dewaxer was combined with a $DIO_3$ rinse to reduce the wax removal time and remove wax residue completely. Replacing DI rinse with the $DIO_3$ rinse resulted in a surface with a contact angle of less than $5^{\circ}$, which indicates no further cleaning steps would be required. The particle removal efficiency (PRE) was further improved by combining a SC-1 cleaning step with the $DIO_3$ rinsing process. A reduction in the process time was obtained by introducing $DIO_3$ cleaning with a dewaxing process.

• Journal of the Microelectronics and Packaging Society
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• v.24 no.4
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• pp.9-17
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• 2017

In these days, MEMS (micro-electro-mechanical system) devices become the crucial sensor components in mobile devices, automobiles and several electronic consumer products. For MEMS devices, the packaging determines the performance, reliability, long-term stability and the total cost of the MEMS devices. Therefore, the packaging technology becomes a key issue for successful commercialization of MEMS devices. As the IoT and wearable devices are emerged as a future technology, the importance of the MEMS sensor keeps increasing. However, MEMS devices should meet several requirements such as ultra-miniaturization, low-power, low-cost as well as high performances and reliability. To meet those requirements, several innovative technologies are under development such as integration of MEMS and IC chip, TSV(through-silicon-via) technology and CMOS compatible MEMS fabrication. It is clear that MEMS packaging will be key technology in future MEMS. In this paper, we reviewed the recent development trends of the MEMS packaging. In particular, we discussed and reviewed the recent technology trends of the MEMS bonding technology, such as low temperature bonding, eutectic bonding and thermo-compression bonding.

• Journal of the Korean Crystal Growth and Crystal Technology
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• v.24 no.5
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• pp.190-195
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• 2014

Because of the temperature gradient occurring during the growth of the ingot with directional solidification method, defects are generated and the residual stress is produced in the ingot. Changing the growth and cooling rate during the crystal growth process will be helpful for us to understand the defects and residual stress generation. The defects and residual stress can affect the properties of wafer. Generally, it was found that the size of grains and twin boundaries are smaller at the top area than at the bottom of the ingot regardless of growth and cooling condition. In addition to that, in the top area of silicon ingot, higher density of dislocation is observed to be present than in the bottom area of the silicon ingot. This observation implies that higher stress is imposed to the top area due to the faster cooling of silicon ingot after solidification process. In the ingot with slower growth rate, dislocation density was reduced and the TTV (Total Thickness Variation), saw mark, warp, and bow of wafer became lower. Therefore, optimum growth condition will help us to obtain high quality silicon ingot with low defect density and low residual stress.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.26 no.11
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• pp.841-845
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• 2013

We give a textured front on silicon wafer for high-efficiency solar cells by using micro contact printing method which uses PDMS (polydimethylsiloxane) silicon rubber as a stamp and SAM (self assembled monolayer)s as an ink. A random pyramidal texturing have been widely used for a front-surface texturing in low cost manufacturing line although the cell with random pyramids on front surface shows relatively low efficiency than the cell with inverted pyramids patterned by normal optical lithography. In the past two decades, the micro contact printing has been intensively studied in nano technology field for high resolution patterns on silicon wafer. However, this promising printing technique has surprisingly never applied so far to silicon based solar cell industry despite their simplicity of process and attractive aspects in terms of cost competitiveness. We employ a MHA (16-mercaptohexadecanoic acid) as an ink for Au deposited $SiO_2/Si$ substrate. The $SiO_2$ pattern which is same as the pattern printed by SAM ink on Au surface and later acts as a hard resist for anisotropic silicon etching was made by HF solution, and then inverted pyramidal pattern is formed after anisotropic wet etching. We compare three textured surface with different morphology (random texture, random pyramids and inverted pyramids) and then different geometry of inverted pyramid arrays in terms of reflectivity.

• Journal of Electrical Engineering and Technology
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• v.5 no.2
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• pp.337-341
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• 2010

In this paper, an extremely low voltage operated micro corner cube retroreflector (CCR) was fabricated for free-space optical communication applications by using bulk silicon micromachining technologies. The CCR was comprised of an orthogonal vertical mirror and a horizontal actuated mirror. For low voltage operation, the horizontal actuated mirror was designed with two PZT cantilever actuators, torsional bars, hinges, and a mirror plate with a size of $400{\mu}m{\times}400{\mu}m$. In particular, the torsional bars and hinges were carefully simulated and designed to secure the flatness of the mirror plate by using a finite element method (FEM) simulator. The measured tilting angle was approximately $2^{\circ}$ at the applied voltage of 5 V. An orthogonal vertical mirror with an extremely smooth surface texture was fabricated using KOH wet etching and a double-SOI (silicon-on-insulator) wafer with a (110) silicon wafer. The fabricated orthogonal vertical mirror was comprised of four pairs of two mutually orthogonal flat mirrors with $400{\mu}m4 (length) $\times400{\mu}m$ (height) $\times30{\mu}m$ (thickness). The cross angles and surface roughness of the orthogonal vertical mirror were orthogonal, almost $90^{\circ}$ and 3.523 nm rms, respectively. The proposed CCR was completed by combining the orthogonal vertical and horizontal actuated mirrors. Data transmission and modulation at a frequency of 10 Hz was successfully demonstrated using the fabricated CCR at a distance of approximately 50 cm.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.18 no.12
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• pp.1106-1110
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• 2005

We fabricated (110) silicon hard master by using anisotropic wet etching for embossing. The etching chemical for the silicon wafer was a TMAH $25\%$ solution. The anisotropic wet etching produces a smooth sidewall surface and the surface roughness of the fabricated master is about 3 nm. After spin coating an organic-inorganic sol-gel hybrid material on a silicon substrate, we employed hot embossing technique operated at a low pressure and temperature to form patterns on the silicon substrate by using the fabricated master. We successfully fabricated the multi-mode planar optical waveguides showing low propagation loss of 0.4 dB/cm. The surface roughness of embossed patterns was uniform for more than 10 times of the embossing processes with a single hydrophobic surface treatment of the silicon hard master.

• Journal of the Semiconductor & Display Technology
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• v.15 no.3
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• pp.57-61
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• 2016

We have studied the structural, optical and electrical properties of IGZO thin films. The IGZO thin films were deposited on the silicon wafer by RF magnetron sputtering method. The RF power in sputtering process was varied as 15W, 30W, 45W, 60W, 75W, respectively. All of the thin films transmittance in the visible range was above 85%. XRD analysis showed that amorphous structure of the thin films without any peak. The Hall measurements in the low RF power is the high mobility above $10cm^2/V{\cdot}s$ and the low resistvity are obtained in the IGZO thin films.