• Title/Summary/Keyword: low phase error

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A Broadband Digital Step Attenuator with Low Phase Error and Low Insertion Loss in 0.18-${\mu}m$ SOI CMOS Technology

  • Cho, Moon-Kyu;Kim, Jeong-Geun;Baek, Donghyun
    • ETRI Journal
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    • v.35 no.4
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    • pp.638-643
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    • 2013
  • This paper presents a 5-bit digital step attenuator (DSA) using a commercial 0.18-${\mu}m$ silicon-on-insulator (SOI) process for the wideband phased array antenna. Both low insertion loss and low root mean square (RMS) phase error and amplitude error are achieved employing two attenuation topologies of the switched path attenuator and the switched T-type attenuator. The attenuation coverage of 31 dB with a least significant bit of 1 dB is achieved at DC to 20 GHz. The RMS phase error and amplitude error are less than $2.5^{\circ}$ and less than 0.5 dB, respectively. The measured insertion loss of the reference state is less than 5.5 dB at 10 GHz. The input return loss and output return loss are each less than 12 dB at DC to 20 GHz. The current consumption is nearly zero with a voltage supply of 1.8 V. The chip size is $0.93mm{\times}0.68mm$, including pads. To the best of the authors' knowledge, this is the first demonstration of a low phase error DC-to-20-GHz SOI DSA.

Measurement of Ratio Error/Phase Angle Error of Potential Transformer using High Voltage Capacitance Bridge and Uncertainty Analysis (고전압 전기용량 브리지를 이용한 전압변성기의 비오차와 위상각 오차의 측정과 불확도 분석)

  • Kwon, Sung-Won;Lee, Sang-Hwa;Kim, Myung-Soo;Jung, Jae-Kap
    • The Transactions of the Korean Institute of Electrical Engineers C
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    • v.55 no.3
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    • pp.134-141
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    • 2006
  • A potential transformer(PT) has ratio error and phase angle error. Precise measurement of the errors of PT can be achieved using high voltage capacitance bridge, high voltage capacitor and low voltage capacitor. The uncertainty for this method is evaluated and found to be $20{\times}10^{-6}$ in both ratio error and phase angle error. The values measured for PT using the method are well consistent with the those measured for same PT in NMIA(National Measurement Institute of Australia) within the corresponding uncertainty.

Effects of the Phase Error on the MTF Characteristics of Binary-phase Hologram Optical Low-pass Filter (컴퓨터로 설계한 2 위상 흘로그램 광 저대역 필터에서 위상차가 필터의 MTF 특성에 미치는 영향)

  • Go, Chun-Soo;Oh, Yong-Ho
    • Journal of the Korean Institute of Electrical and Electronic Material Engineers
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    • v.18 no.8
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    • pp.739-746
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    • 2005
  • When we design a binary phase holographic optical low-pass filter (HOLF), the phase difference is generally set to be $\pi$ to optimize the diffraction efficiency. However, the phase difference of real HOLF mostly deviate from $\pi$ by the error in the fabrication process. The deviation causes the (0,0)-th order diffracted beam to increase, which results In raising the diffraction efficiency. To study the effects of the phase error on the performance of HOLF, we calculated the MTF of HOLF for various phase differences. The results show that the phase error of 10 $\%$ makes little change in the filtering characteristics of HOLF. Considering the filtering by lens and CCD, the effects of the phase error becomes much smaller. To confirm it experimentally, we fabricated HOLFs for various phase differences. After installing it in a digital camera, we take picture of test targets and observe the Moire fringes and the resolution. The results agree with our prediction.

Location Error Analysis of an Active RFID-Based RTLS in Multipath and AWGN Environments

  • Myong, Seung-Il;Mo, Sang-Hyun;Yang, Hoe-Sung;Cha, Jong-Sub;Lee, Heyung-Sub;Seo, Dong-Sun
    • ETRI Journal
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    • v.33 no.4
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    • pp.528-536
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    • 2011
  • In this paper, we analyze the location accuracy of real-time locating systems (RTLSs) in multipath environments in which the RTLSs comply with the ISO/IEC 24730-2 international standard. To analyze the location error of RTLS in multipath environments, we consider a direct path and indirect path, in which time and phase are delayed, and also white Gaussian noise is added. The location error depends strongly on both the noise level and phase difference under a low signal-to-noise ratio (SNR) regime, but only on the noise level under a high SNR regime. The phase difference effect can be minimized by matching it to the time delay difference at a ratio of 180 degrees per 1 chip time delay (Tc). At a relatively high SNR of 10 dB, a location error of less than 3 m is expected at any phase and time delay value of an indirect signal. At a low SNR regime, the location error range increases to 8.1 m at a 0.5 Tc, and to 7.3 m at a 1.5 Tc. However, if the correlation energy is accumulated for an 8-bit period, the location error can be reduced to 3.9 m and 2.5 m, respectively.

Effects of LDPC Code on the BER Performance of MPSK System with Imperfect Receiver Components over Rician Channels

  • Djordjevic, Goran T.;Djordjevic, Ivan B.;Ivanis, Predrag N.
    • ETRI Journal
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    • v.31 no.5
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    • pp.619-621
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    • 2009
  • In this letter, we study the influence of receiver imperfections on bit error rate (BER) degradations in detecting low-density parity-check coded multilevel phase-shift keying signals transmitted over a Rician fading channel. Based on the analytical system model which we previously developed using Monte Carlo simulations, we determine the BER degradations caused by the simultaneous influences of stochastic phase error, quadrature error, in-phase-quadrature mismatch, and the fading severity.

A Study on Measurement Method of Optical Path Error in Arrayed Waveguide Grating Router (광도파로열 격자 라우터의 경로오차 측정 방법에 관한 연구)

  • Park, Jae-Sung;Chung, Young-Chul;Mun, Seong-Uk
    • Proceedings of the KIEE Conference
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    • 1999.07e
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    • pp.2431-2433
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    • 1999
  • Phase errors of arrayed waveguide degrade the performance of AWG router, especially for dense WDM system. So it is necessary to measure the phase error and to compensate. The analysis method of the interference signal from the low coherence interferometer to measure the path length difference phase error is studied. The interference signal generated assuming the intentional path length difference errors of 0.1$\sim$0.4${\mu}m$ are analyzed and the results show that the path length difference phase error of ${\Delta}L$ within ${\pm}14^{\circ}$ of sampling phase error can be accurately measured.

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Digital Control of a Single-Phase UPS Inverter for Robust AC-Voltage Tracking

  • Woo Young-Tae;Kim Young-Chol
    • International Journal of Control, Automation, and Systems
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    • v.3 no.4
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    • pp.620-630
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    • 2005
  • This paper presents a digital controller for a single phase UPS inverter under two main considerations: (i) the overall system shall keep very low AC-voltage tracking error as well as no phase delay over different load conditions, and (ii) the digital controller shall be employed at a fixed sampling time. We propose that the former can be achieved by the proposed controller using the error-state approach and the latter can be dealt with by the socalled characteristics ration assignment.

A Low Jitter and Fast Locking Phase-Lock Loop with Adaptive Bandwidth Controller

  • Song Youn-Gui;Choi Young-Shig
    • Journal of information and communication convergence engineering
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    • v.3 no.1
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    • pp.18-22
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    • 2005
  • This paper presents the analog adaptive phase-locked loop (PLL) architecture with a new adaptive bandwidth controller to reduce locking time and minimize jitter in PLL output for wireless communication. It adaptively controls the loop bandwidth according to the locking status. When the phase error is large, the PLL increases the loop bandwidth and reduces locking time. When the phase error is small, the PLL decreases the loop bandwidth and minimizes output jitters. The adaptive bandwidth control is implemented by controlling charge pump current depending on the locking status. A 1.28-GHz CMOS phase-locked loop with adaptive bandwidth control is designed with 0.35 $mu$m CMOS technology. It is simulated by HSPICE and achieves the primary reference sidebands at the output of the VCO are approximately -80dBc.

Design and Performance Analysis of Nonbinary LDPC Codes With Low Error-Floors (오류 마루 현상이 완화된 비이진 LDPC 부호의 설계 및 성능 분석 연구)

  • Ahn, Seok-Ki;Lim, Seung-Chan;Yang, Youngoh;Yang, Kyeongcheol
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.38C no.10
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    • pp.852-857
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    • 2013
  • In this paper we propose a design algorithm for nonbinary LDPC (low-density parity-check) codes with low error-floors. The proposed algorithm determines the nonbinary values of the nonzero entries in the parity-check matrix in order to maximize the binary minimum distance of the designed nonbinary LDPC codes. We verify the performance of the designed nonbinary LDPC codes in the error-floor region by Monte Carlo simulation and importance sampling over BPSK (binary phase-shift keying) modulation.

Phase Offset Enumeration Method with Error Detection and Its Application to Synchronization of PN Sequences

  • Song Young-Joan
    • Journal of electromagnetic engineering and science
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    • v.5 no.1
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    • pp.26-30
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    • 2005
  • It is important to know phase offsets of PN(Pseudo Noise) sequences in spread spectrum communications since the acquisition is equivalent to making a phase offset between a receiving PN sequence and a PN sequence of local PN generator be identical. In this paper, a phase offset enumeration method for PN sequences with error detection, and its application to the synchronization are proposed. The phase offset enumeration for an n-tuple PN sequence and its error detection are performed when one period of the sequence is received. Once the phase offset of the receiving sequence is calculated, we can easily accomplish the synchronization by initializing shift registers of a local PN generator according to the phase offset value. The mean acquisition time performance of the proposed scheme was derived analytically. Since this synchronization scheme can be realized by using simple circuit and acquires very rapid acquisition in high SNR but shows performance degradation in low SNR, it can be especially useful in indoor and office environments.