• Title/Summary/Keyword: long-memory

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Real-Time Digital Image Stabilization for Cell Phone Cameras in Low-Light Environments without Frame Memory

  • Luo, Lin-Bo;Chong, Jong-Wha
    • ETRI Journal
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    • v.34 no.1
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    • pp.138-141
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    • 2012
  • This letter proposes a real-time digital image stabilization system for cell phone cameras without the need for frame memory. The system post-processes an image captured with a safe shutter speed using an adaptive denoising filter and a global color correction algorithm. This system can transfer the normal brightness of an image previewed under long exposure to the captured image making it bright and crisp with low noise. It is even possible to take photos in low-light conditions. By not needing frame memory, the approach is feasible for integration into the size-constrained image sensors of cell phone cameras.

A Low Power Design of H.264 Codec Based on Hardware and Software Co-design

  • Park, Seong-Mo;Lee, Suk-Ho;Shin, Kyoung-Seon;Lee, Jae-Jin;Chung, Moo-Kyoung;Lee, Jun-Young;Eum, Nak-Woong
    • Information and Communications Magazine
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    • v.25 no.12
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    • pp.10-18
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    • 2008
  • In this paper, we present a low-power design of H.264 codec based on dedicated hardware and software solution on EMP(ETRI Multi-core platform). The dedicated hardware scheme has reducing computation using motion estimation skip and reducing memory access for motion estimation. The design reduces data transfer load to 66% compared to conventional method. The gate count of H.264 encoder and the performance is about 455k and 43Mhz@30fps with D1(720x480) for H.264 encoder. The software solution is with ASIP(Application Specific Instruction Processor) that it is SIMD(Single Instruction Multiple Data), Dual Issue VLIW(Very Long Instruction Word) core, specified register file for SIMD, internal memory and data memory access for memory controller, 6 step pipeline, and 32 bits bus width. Performance and gate count is 400MHz@30fps with CIF(Common Intermediated format) and about 100k per core for H.264 decoder.

Mathematical thinking, its neural systems and implication for education (수학적 사고에 동원되는 두뇌 영역들과 이의 교육학적 의미)

  • Kim, Yeon Mi
    • The Mathematical Education
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    • v.52 no.1
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    • pp.19-41
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    • 2013
  • What is the foundation of mathematical thinking? Is it logic based symbolic language system? or does it rely more on mental imagery and visuo-spatial abilities? What kind of neural changes happen if someone's mathematical abilities improve through practice? To answer these questions, basic cognitive processes including long term memory, working memory, visuo-spatial perception, number processes are considered through neuropsychological outcomes. Neuronal changes following development and practices are inspected and we can show there are neural networks critical for the mathematical thinking and development: prefrontal-anterior cingulate-parietal network. Through these inquiry, we can infer the answer to our question.

A Hierarchical Binary-search Tree for the High-Capacity and Asymmetric Performance of NVM (비대칭적 성능의 고용량 비휘발성 메모리를 위한 계층적 구조의 이진 탐색 트리)

  • Jeong, Minseong;Lee, Mijeong;Lee, Eunji
    • IEMEK Journal of Embedded Systems and Applications
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    • v.14 no.2
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    • pp.79-86
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    • 2019
  • For decades, in-memory data structures have been designed for DRAM-based main memory that provides symmetric read/write performances and has no limited write endurance. However, such data structures provide sub-optimal performance for NVM as it has different characteristics to DRAM. With this motivation, we rethink a conventional red-black tree in terms of its efficacy under NVM settings. The original red-black tree constantly rebalances sub-trees so as to export fast access time over dataset, but it inevitably increases the write traffic, adversely affecting the performance for NVM with a long write latency and limited endurance. To resolve this problem, we present a variant of the red-black tree called a hierarchical balanced binary search tree. The proposed structure maintains multiple keys in a single node so as to amortize the rebalancing cost. The performance study reveals that the proposed hierarchical binary search tree effectively reduces the write traffic by effectively reaping the high capacity of NVM.

A Study on the Original Symbols in Lee Chung-jun's novel Snowy Road

  • Park, Hae Rang
    • International Journal of Advanced Culture Technology
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    • v.10 no.2
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    • pp.92-97
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    • 2022
  • This study studied the seasons in the novel Snowy Read and the archetypal characteristics in natural phenomena. Summer and winter are the main seasons of Snowy Road. The cycle of the day is the time of dawn and early morning, evening, or night. It is summer now, and memory day is winter. In Snowy Road, 'I' is in sharp conflict with my mom during the summer season. This conflict is resolved and resurfaced with the feeling of 'love' as the story of the day is told in the mother's memory. It was a long time of conflict and trials for winter in the memory of me and my mother. As a result of examining the circular symbols in the Snowy Road, each symbol represents the 'I' and 'the mother's feelings'. 'I' and 'Mom's Emotions' collide, but they confirm each other's sincerity and rebuild their feelings of conflict with 'love'. In Snowy Road, the mother and son's 'love' shows that the mother's son is deeply in love, but the son's mother's love is also very deep.

EPET-WL: Enhanced Prediction and Elapsed Time-based Wear Leveling Technique for NAND Flash Memory in Portable Devices

  • Kim, Sung Ho;Kwak, Jong Wook
    • Journal of the Korea Society of Computer and Information
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    • v.21 no.5
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    • pp.1-10
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    • 2016
  • Magnetic disks have been used for decades in auxiliary storage devices of computer systems. In recent years, the use of NAND flash memory, which is called SSD, is increased as auxiliary storage devices. However, NAND flash memory, unlike traditional magnetic disks, necessarily performs the erase operation before the write operation in order to overwrite data and this leads to degrade the system lifetime and performance of overall NAND flash memory system. Moreover, NAND flash memory has the lower endurance, compared to traditional magnetic disks. To overcome this problem, this paper proposes EPET (Enhanced Prediction and Elapsed Time) wear leveling technique, which is especially efficient to portable devices. EPET wear leveling uses the advantage of PET (Prediction of Elapsed Time) wear leveling and solves long-term system failure time problem. Moreover, EPET wear leveling further improves space efficiency. In our experiments, EPET wear leveling prolonged the first bad time up to 328.9% and prolonged the system lifetime up to 305.9%, compared to other techniques.

Memory-saving Real-time Collaborative Editing System using Valid-Time Operational Transformation (유효시간 운영변환을 이용한 메모리 절약형 실시간 협업 편집 시스템)

  • Kwon, Oh-Seok;Kim, Young-Bong;Kwon, Oh-Jun;Lee, Suk-Hwan;Kwon, Ki-Ryong
    • Journal of Korea Multimedia Society
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    • v.21 no.2
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    • pp.232-241
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    • 2018
  • Operational Transformation (OT) algorithms for real-time collaborative editing systems are becoming increasingly important due to the increased demand for collaborative data processing. The operational transformation algorithm is a technique for real-time concurrency control and consistency maintenance with non-locking technique, and many studies have been conducted to overcome three issues of convergence, causality-prevention, and intention-prevention. However, previous work has the disadvantage of wasting memory by storing all operations that occurred during an edit operation in the history buffer to solve this problem. Therefore, we propose a memory-saving real-time collaborative editing system that maintains a constant memory space and concurrency control through a method of applying the valid-time to each user-generated operation in order to reduce memory waste. This system prevents long-term memory occupation of client-generated operations, thus it reduces the space and time complexity even with low-rate of collaboration work, so that the performance degradation avoids.

Strengthened connections between engrams encode specific memories

  • Kim, Ji-il;Choi, Dong Il;Kaang, Bong-Kiun
    • BMB Reports
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    • v.51 no.8
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    • pp.369-370
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    • 2018
  • In previous studies, memory storage was localized to engram cells distributed across the brain. While these studies have provided an individual cellular profile of engram cells, their synaptic connectivity, or whether they follow Hebbian mechanisms, remains uncertain. Therefore, our recent study investigated whether synapses between engram cells exhibit selectively enhanced structural and functional properties following memory formation. This was accomplished using a newly developed technique called "dual-eGRASP". We found that the number and size of spines on CA1 engram cells that receive inputs from CA3 engram cells were larger than at other synapses. We further observed that this enhanced connectivity correlated with induced memory strength. CA3 engram synapses exhibited increased release probability, while CA1 engram synapses produced enhanced postsynaptic responses. CA3 engram to CA1 engram projections showed strong occlusion of long-term potentiation. We demonstrated that the synaptic connectivity of CA3 to CA1 engram cells was strengthened following memory formation. Our results suggest that Hebbian plasticity occurs during memory formation among engram cells at the synapse level.

Improvement in Memory Characteristics of Charge Trap Memory Capacitor with High-k Materials as Engineered Tunnel Dielectrics and Charge Trap Layer (엔지니어드된 터널 절연막과 전하트랩층에 고유전 물질을 적용한 전하 트랩형 메모리 캐패시터의 메모리 특성 개선)

  • Kim, Min-Soo;You, Hee-Wook;Park, Goon-Ho;Oh, Se-Man;Jung, Jong-Wan;Lee, Young-Hie;Chung, Hong-Bay;Cho, Won-Ju
    • Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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    • 2009.06a
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    • pp.408-409
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    • 2009
  • The memory characteristics of charge trap memory capacitor with high-k materials were investigated. I-V characteristics of the fabricated device with band gap engineered tunneling gate stacks consisted of $SiO_2$, $ZrO_2$, $Al_2O_3$ dielectrics were evaluated and compared with the one consisted of $SiO_2$ tunneling dielectric. The memory capacitor including engineered tunneling dielectrics of ($Al_2O_3/ZrO_2/SiO_2$) shows the fastest PIE speed and long data retention time.

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LDF-CLOCK: The Least-Dirty-First CLOCK Replacement Policy for PCM-based Swap Devices

  • Yoo, Seunghoon;Lee, Eunji;Bahn, Hyokyung
    • JSTS:Journal of Semiconductor Technology and Science
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    • v.15 no.1
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    • pp.68-76
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    • 2015
  • Phase-change memory (PCM) is a promising technology that is anticipated to be used in the memory hierarchy of future computer systems. However, its access time is relatively slower than DRAM and it has limited endurance cycle. Due to this reason, PCM is being considered as a high-speed storage medium (like swap device) or long-latency memory. In this paper, we adopt PCM as a virtual memory swap device and present a new page replacement policy that considers the characteristics of PCM. Specifically, we aim to reduce the write traffic to PCM by considering the dirtiness of pages when making a replacement decision. The proposed replacement policy tracks the dirtiness of a page at the granularity of a sub-page and replaces the least dirty page among pages not recently used. Experimental results with various workloads show that the proposed policy reduces the amount of data written to PCM by 22.9% on average and up to 73.7% compared to CLOCK. It also extends the lifespan of PCM by 49.0% and reduces the energy consumption of PCM by 3.0% on average.