• Journal of the Institute of Electronics Engineers of Korea SC
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• v.43 no.4 s.310
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• pp.45-52
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• 2006

In his paper, we have developed the SMD(surface mounted device) type PECL(positive emitter-coupled logic) VCXO of the $5{\times}7mm$ size for gratifying the requested specifications and the multilayer ceramic SMD(surface mounted device) package technology. The VCXO wired with the PECL(positive emitter coupled logic) package take place a stray inductance and a parasitic capacitance by the length and the inner pattern of the VCXO and the amplitude attenuation and signal loss due to the reflection of power source and the noise component. We have developed the Zig system to analyze the precise spectrum and evaluate the performance. The basic operating voltage is the 3.3 V and have the frequency range of 120MHz-180MHz. The Q factor is over 5K and it has the low jitter characteristics of 3.5 ps and low phase noise.

• Journal of Semiconductor Engineering
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• v.1 no.1
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• pp.57-63
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• 2020

Complementary metal-oxide-semiconductor (CMOS) technology is now facing a power scaling limit to increase integration density. Since 1970s, multi-valued logic (MVL) has been considered as promising alternative to resolve power scaling challenge for increasing information density up to peta-scale level by reducing the system complexity. Over the past several decades, however, a power-scalable and mass-producible MVL technology has been absent so that MVL circuit and system implementation have been delayed. Recently, compact MVL device researches incorporating multiple-switching characteristics in a single device such as 2D heterojunction-based negative-differential resistance (NDR)/transconductance (NDT) devices and quantum-dot/superlattices-based constant intermediate current have been actively performed. Meanwhile, wafer-scale, energy-efficient and variation-tolerant ternary-CMOS (T-CMOS) technology has been demonstrated through commercial foundry. In this review paper, an overview for MVL development history including recent studies will be presented. Then, the status and its future research direction of MVL technology will be discussed focusing on the T-CMOS technology for peta-scale information processing in semiconductor chip.

• Proceedings of the Korea Institute of Convergence Signal Processing
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• 2000.12a
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• pp.209-212
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• 2000

This paper describes the design and implementation of a hard- wired AGV controller using CPLD(Complex Programmable Logic Device). The proposed controller manages a guidance equipment, motor and I/O sequence controller for a self-control traveling. Compared with a conventional $\mu$-processor, the CPLD controller using a hard-wired control method can reduce a difficult programming process. Also, the total costs of production are reduced, such as development time, product's size and difficulty because memory, combinational logic and sequential logics are implemented by CPLD. The Controller designed using behavioral description method with VHDL and was synthesized by MAX＋Plus II of the ALTERA co. We implemented controller using EPF10K10LC84-4 device.

• Communications for Statistical Applications and Methods
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• v.8 no.2
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• pp.465-471
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• 2001

Randomized response technique is a survey technique for eliminating evasive answer bias. But this technique has a problem. This procedure suffers from linguistic expression in randomizing device. Thus for solving the problem, in this paper, we suggested the randomized response technique using fuzzy logic.

• 제어로봇시스템학회:학술대회논문집
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• 1996.10b
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• pp.486-489
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• 1996

The objective of this paper is to design a force feedback controller for bilateral control of a master-slave manipulator system. In a bilateral control system, the motion of the master device is followed by the slave one, while the force applied to the slave is reflected on the master. In this paper, a fuzzy logic controllers applied to the system. Using the fuzzy logic controller, the knowledge of the system dynamics is not needed. Simulations and experimental results show the performance of the proposed controller.

• The Proceeding of the Korean Institute of Electromagnetic Engineering and Science
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• v.24 no.2
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• pp.51-57
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• 2013

The current expanding mobile markets incessantly demands small form factor, low power consumption and high aggregate throughput for silicon-level integration such as memory to logic system. One of emerging solution for meeting this high market demand is 3D through silicon stacking (TSS) technology. Main challenges to bring 3D TSS technology to the volume production level are establishing a cost effective supply chain and building a reliable manufacturing processes. In addition, this technology inherently help increase number of IOs and shorten interconnect length. With those benefits, however, potential signal and power integrity risks are also elevated; increase in PDN inductance, channel loss on substrate, crosstalk and parasitic capacitance. This paper will report recent progress of wide IO memory to high count TSV logic device assembly development work. 28 nm node TSV test vehicles were fabricated by the foundry and assembled. Successful integration of memory wide IO chip with less than a millimeter package thickness form factor was achieved. For this successful integration, we discussed potential signal and power integrity challenges. This report demonstrated functional wide IO memory to 28 nm logic device assembly using 3D package architecture with such a thin form factor.

• Journal of the Korean Society of Industry Convergence
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• v.5 no.1
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• pp.39-43
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• 2002

In present much CMOS devices used in VLSI circuit and Logic circuit. With increasing a number of device in VLSI, the confidence becomes more serious. This paper describe the mechanism of breakdown on CMOS, especially n-MOS, based on Hydro Dynamic model with device self-heating. Additionally, illustrate the CMOS latch-up characteristics on simplified device structure on this paper.

• Proceedings of the KIEE Conference
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• 1998.07g
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• pp.2327-2329
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• 1998

In this paper, an algorithm to make a configuration system for managing the I/O device of programmable logic controller(PLC) is proposed. Parallel processing architecture is used to deal with a number of I/O devices. From that architecture, a contention problem between processors can arise. To resolve this problem, the configuration system that contains informations about I/O devices is introduced. This configuration system is used to check the contention between processors in the I/O device and also used in program execution.

• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.18 no.6
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• pp.45-54
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• 2004

Usually, according as accumulation degree of semi-conductor element increases, dynamic mistake test time increases sharply, and use of pattern generator is essential at manufacturing process to solve these problem. In this paper, we designed the PLD(Programmable Logic Device) circuit of pattern generator to examine dynamic mistake of semi-conductor element. Such all item got result that is worth verified action of return trip and function through simulation, and satisfy.

• ETRI Journal
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• v.26 no.6
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• pp.669-672
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• 2004

To improve the operation error caused by the thermal fluctuation of electrons, we propose a novel single-electron pass-transistor logic circuit employing a multiple-tunnel junction (MTJ) scheme and modulate a parameters of an MTJ single-electron tunneling device (SETD) such as the number of tunnel junctions, tunnel resistance, and voltage gain. The operation of a 3-MTJ inverter circuit is simulated at 15 K with parameters $C_g=C_T=C_{clk}=1\;aF,\;R_T=5\;M{\Omega},\;V_{clk}=40\;mV$, and $V_{in}=20\;mV$. Using the SETD/MOSFET hybrid circuit, the charge state output of the proposed MTJ-SETD logic is successfully translated to the voltage state logic.