Through Silicon Stack (TSS) Assembly for Wide IO Memory to Logic Devices Integration and Its Signal Integrity Challenges

  • Published : 2013.03.31

Abstract

The current expanding mobile markets incessantly demands small form factor, low power consumption and high aggregate throughput for silicon-level integration such as memory to logic system. One of emerging solution for meeting this high market demand is 3D through silicon stacking (TSS) technology. Main challenges to bring 3D TSS technology to the volume production level are establishing a cost effective supply chain and building a reliable manufacturing processes. In addition, this technology inherently help increase number of IOs and shorten interconnect length. With those benefits, however, potential signal and power integrity risks are also elevated; increase in PDN inductance, channel loss on substrate, crosstalk and parasitic capacitance. This paper will report recent progress of wide IO memory to high count TSV logic device assembly development work. 28 nm node TSV test vehicles were fabricated by the foundry and assembled. Successful integration of memory wide IO chip with less than a millimeter package thickness form factor was achieved. For this successful integration, we discussed potential signal and power integrity challenges. This report demonstrated functional wide IO memory to 28 nm logic device assembly using 3D package architecture with such a thin form factor.

Keywords

References

  1. S. Q. Gu et al., "Stackable memory of 3D chip integration for mobile applications", IEDM Tech. Dig., 2008.
  2. J. West, et al., "Practical implications of via-middle Cu TSV-induced stress in a 28 nm CMOS technology for wide-IO logic-memory interconnect", Symposium on VLSI Technology, art. no. 6242481, pp. 101-102, 2012.
  3. U. H. Kang et al., "8Gb 3D DDR DRAM using TSV technology", IEEE Journal of Solid State Circuits, vol. 45, no. 1, pp. 111-119, Jan. 2010. https://doi.org/10.1109/JSSC.2009.2034408
  4. J. S. Pak, et al., "PDN impedance modeling and analysis of 3D TSV IC by using proposed P/G TSV array model based on separated P/G TSV and chip- PDN models", Components, Packaging and Manufacturing Technology, IEEE Transactions on, vol. 1, no. 2, pp. 208, 219, Feb. 2011.
  5. J. S. Pak, et al., "TSV mutual inductance effect on impedance of 3D stacked on-chip PDN with multi- TSV connections", CPMT Symposium Japan, 2010 IEEE, pp. 1, 4, 24-26 Aug. 2010.
  6. L. Zhang, et al., "Achieving Stable Through-Silicon Via (TSV) capacitance with oxide fixed charge", Electron Device Letters, IEEE, vol. 32, no. 5, pp. 668, 670, May 2011.
  7. Z. Xu, et al., "Crosstalk evaluation, suppression and modeling in 3D through-strata-via (TSV) network", 3D Systems Integration Conference (3DIC), 2010 IEEE International, pp. 1, 8, 16-18 Nov. 2010.
  8. J. Cho, et al., "Modeling and analysis of Through- Silicon Via (TSV) noise coupling and suppression using a guard ring", Components, Packaging and Manufacturing Technology, IEEE Transactions on, vol. 1, no. 2, pp. 220, 233, Feb. 2011.
  9. H. Kim, et al., "Measurement and analysis of a high-speed TSV channel", Components, Packaging and Manufacturing Technology, IEEE Transactions on, vol. 2, no. 10, pp. 1672, 1685, Oct. 2012.