• Journal of the Institute of Electronics Engineers of Korea SC
• /
• v.44 no.1
• /
• pp.74-84
• /
• 2007

This paper presents a new dual-loop Delay Locked Loop(DLL) to expand the delay lock range of a conventional DLL. The proposed dual-loop DLL contains a Coarse_loop and a Fine_loop, and its operation utilizes one of the loops selected by comparing the initial time-difference among the reference clock and 2 internal clocks. The 2 internal clock signals are taken, respectively, at the midpoint and endpoint of a VCDL and thus are $180^{\circ}$ separated in phase. When the proposed DLL is out of the conventional lock range, the Coarse_loop is selected to push the DLL in the conventional lock range and then the Fine_loop is used to complete the locking process. Therefore, the proposed DLL is always stably locked in unless it is harmonically false-locked. Since the VCDL employed in the proposed DLL needs two control voltages to adjust the delay time, it uses TG-based inverters, instead of conventional, multi-stacked, current-starved inverters, to compose the delay line. The new VCDL provides a wider delay range than a conventional VCDL In overall, the proposed DLL demonstrates a more than 2 times wider lock range than a conventional DLL. The proposed DLL circuits have been designed, simulated and proved using 0.18um, 1.8V TSMC CMOS library and its operation frequency range is 100MHz${\sim}$1GHz. Finally, the maximum phase error of the DLL locked in at 1GHz is less than 11.2ps showing a high resolution and the simulated power consumption is 11.5mW.

• Journal of the Institute of Electronics and Information Engineers
• /
• v.50 no.9
• /
• pp.46-51
• /
• 2013

In this paper, the optimum placement and shape of UHF antenna on the unmanned aerial vehicle (UAV) are analyzed by using the electromagnetic (EM) simulation on the various locations. The FEKO was used for the EM-simulation. In order to reduce the complexity of simulation and minimize the runtime and memory usage, the composite aircraft structure is simplified as the PEC model excluding the radome structure. The simulation was performed on the wing and ventral fin of UAV, and the antenna shape used the monopole, dipole, and bent monopole antennas. When the monopole antenna is mounted under the wing, two antennas need to be mounted under the right and left wings, and those antennas have to be switched as the direction of UAV wing to the line of sight (LOS) data-link (DL) ground antenna. In the case of mounting under the ventral fin, one antenna can be used regardless of the direction of UAV wing to the LOS DL ground antenna. Also, the antenna gain is improved by the blockage reduction. The antenna gain is further improved by using the bent monopole antenna. The optimum solution of UHF antenna placement and shape on UAV is to mount the bent monopole antenna under the ventral fin.

• The Journal of the Korea Contents Association
• /
• v.13 no.11
• /
• pp.322-331
• /
• 2013

The purpose of the present study was to develop a convergent education contents for dementia prevention, operating on the web network applying modern information technology(IT). At the preparation stage, local and worldwide literatures related to dementia were analyzed followed by surveying industry demands, based on which the program was designed and developed. In the following enhancement stage, the program was modified as much as possible by advices obtained from experts in various fields. Development results of the present program are summarized as follows. Firstly, 645 intellect development model to prevent dementia was established through peer review and verification of convergent education theories by expert groups. This model was named as "Garisani" meaning "cognition capable of judging objects" in the Korean language. Secondly, 'Find a way' and 'Connect a line' modules were developed in the numeric field as well as 'Identify a letter(I, II)' modules, in the language field for web-based left brain training program. Thirdly, 'Find my car' and 'Vision training' modules in the attention field and 'Object inference' and 'Compare pictures' modules in the cognition field were developed for web-based right brain training program. Fourth, 'Pentomino' and 'BQmaze'(Brain Quotient and maze) modules in the space perception field and 'Visual training' in the memory field were developed for web-based left and right brains training. Fifth, all results were integrated leading to a 52 week Garisani convergent education program for dementia prevention.

• The KIPS Transactions:PartD
• /
• v.13D no.4 s.107
• /
• pp.463-476
• /
• 2006

R-trees have been traditionally optimized for the I/O performance with the disk page as the tree node. Recently, researchers have proposed cache-conscious variations of R-trees optimized for the CPU cache performance in main memory environments, where the node size is several cache lines wide and more entries are packed in a node by compressing MBR keys. However, because there is a big difference between the node sizes of two types of R-trees, disk-optimized R-trees show poor cache performance while cache-optimized R-trees exhibit poor disk performance. In this paper, we propose a cache and disk optimized R-tree, called the PR-tree (Prefetching R-tree). For the cache performance, the node size of the PR-tree is wider than a cache line, and the prefetch instruction is used to reduce the number of cache misses. For the I/O performance, the nodes of the PR-tree are fitted into one disk page. We represent the detailed analysis of cache misses for range queries, and enumerate all the reasonable in-page leaf and nonleaf node sizes, and heights of in-page trees to figure out tree parameters for best cache and I/O performance. The PR-tree that we propose achieves better cache performance than the disk-optimized R-tree: a factor of 3.5-15.1 improvement for one-by-one insertions, 6.5-15.1 improvement for deletions, 1.3-1.9 improvement for range queries, and 2.7-9.7 improvement for k-nearest neighbor queries. All experimental results do not show notable declines of the I/O performance.

• Journal of KIISE:Computer Systems and Theory
• /
• v.26 no.9
• /
• pp.1083-1095
• /
• 1999

최근 처리기와 입출력 시스템의 속도 차이가 점점 커짐에 따라 버퍼 캐쉬의 효율적인 관리가 더욱 중요해지고 있다. 버퍼 캐쉬는 블록 교체 정책과 선반입 정책에 의해 관리되며, 각 정책은 버퍼 캐쉬에서 블록의 가치 즉 어떤 블록이 더 가까운 미래에 참조될 것인가를 결정해야 한다. 블록의 가치는 응용들의 블록 참조 패턴의 특성에 기반하며, 블록 참조 패턴의 특성에 대한 정확한 분석은 올바른 결정을 가능하게 하여 버퍼 캐쉬의 효율을 높일 수 있다. 본 논문은 각 응용들의 블록 참조 패턴에 대한 특성을 분석하고 이를 자동으로 발견하는 기법을 제안한다. 제안된 기법은 블록의 속성과 미래 참조 거리간의 관계를 이용해 블록 참조 패턴을 발견한다. 이 기법은 2 단계 파이프라인 방법을 이용하여 온라인으로 참조 패턴을 발견할 수 있으며, 참조 패턴의 변화가 발생하면 이를 인식할 수 있다. 본 논문에서는 8개의 실제 응용 트레이스를 이용해 블록 참조 패턴의 발견을 실험하였으며, 제안된 기법이 각 응용의 블록 참조 패턴을 정확히 발견함을 확인하였다. 그리고 발견된 참조 패턴 정보를 블록 교체 정책에 적용해 보았으며, 실험 결과 기존의 대표적인 블록 교체 정책인 LRU에 비해 최대 57%까지 디스크 입출력 횟수를 줄일 수 있었다.Abstract As the speed gap between processors and disks continues to increase, the role of the buffer cache located in main memory is becoming increasingly important. The buffer cache is managed by block replacement policies and prefetching policies and each policy should decide the value of block, that is which block will be accessed in the near future. The value of block is based on the characteristics of block reference patterns of applications, hence accurate characterization of block reference patterns may improve the performance of the buffer cache. In this paper, we study the characteristics of block reference behavior of applications and propose a scheme that automatically detects the block reference patterns. The detection is made by associating block attributes of a block with the forward distance of the block. With the periodic detection using a two-stage pipeline technique, the scheme can make on-line detection of block reference patterns and monitor the changes of block reference patterns. We measured the detection capability of the proposed scheme using 8 real workload traces and found that the scheme accurately detects the block reference patterns of applications. Also, we apply the detected block reference patterns into the block replacement policy and show that replacement policies appropriate for the detected block reference patterns decreases the number of DISK I/Os by up to 57%, compared with the traditional LRU policy.

• Korean Journal of Remote Sensing
• /
• v.31 no.5
• /
• pp.395-408
• /
• 2015

High-resolution satellite image mosaics are becoming increasingly important in the field of remote sensing image analysis as an essential image processing to create a large image constructed from several smaller images. In this paper, we present an automatic seamline extraction technique and the procedure to generate a mosaic image by this technique. For more effective seamline extraction in the overlap region of adjacent images, an NDVI-based seamline extraction technique is developed, which takes advantage of the computational time and memory. The Normalized Difference Vegetation Index(NDVI) is an index of plant "greeness" or photosynthetic activity that is employed to extract the initial seamline. The NDVI can divide into manmade region and natural region. The cost image is obtained by the canny edge detector and the buffering technique is used to extract the ranging cost image. The seamline is extracted by applying the Dijkstra algorithm to a cost image generated through the labeling process of the extracted edge information. Histogram matching is also conducted to alleviate radiometric distortion between adjacent images acquired at different time. In the experimental results using the KOMPSAT-2/3 satellite imagery, it is confirmed that the proposed method greatly reduces the visual discontinuity caused by geometric difference of adjacent images and the computation time.

• Korean Journal of Materials Research
• /
• v.10 no.12
• /
• pp.812-818
• /
• 2000

We studied the effects of Ge preamorphization (PAM) on 0.25$\mu\textrm{m}$ Ti-salicide junctions using comparative study with As PAM. For each PAM schemes, ion implantations are performed at a dose of 2E14 ion/$\textrm{cm}^2$ and at 20keV energy using $^{75}$ /As+and GeF4 ion sources. Ge PAM showed better sheet resistance and within- wafer uniformity than those of As PAM at 0.257m line width of n +/p-well junctions. This attributes to enhanced C54-silicidation reaction and strong (040) preferred orientation of the C54-silicide due to minimized As presence at n+ junctions. At p+ junctions, comparable performance was obtained in Rs reduction at fine lines from both As and Ge PAM schemes. Junction leakage current (JLC) revels are below ~1E-14 A/$\mu\textrm{m}^{2}$ at area patterns for all process conditions, whereas no degradation in JLC is shown under Ge PAM condition even at edge- intensive patterns. Smooth $TiSi_2$ interface is observed by cross- section TEM (X- TEM), which supports minimized silicide agglomeration due to Ge PAM and low level of JLC. Both junction break- down voltage (JBV) and contact resistances are satisfactory at all process conditions.

• Journal of the Institute of Electronics Engineers of Korea SP
• /
• v.49 no.1
• /
• pp.19-30
• /
• 2012

For digital data compression, the quantization is the main part of the lossy source coding. In order to improve the performance of quantization, the vector quantizer(VQ) can be employed. The encoding complexity, however, exponentially increases as the vector dimension or bit rate gets large. Much research has been conducted to alleviate such problems of VQ. Especially for high bit rates, a constrained VQ, which is called the sample-adaptive product quantizer(SAPQ), has been proposed for reducing the hugh encoding complexity of regular VQs. SAPQ has very similar structure as to the product VQ(PQ). However, the quantizer performance can be better than the PQ case. Further, the encoding complexity and the memory requirement for the codebooks are lower than the regular full-search VQ case. Among SAPQs, 1-SAPQ has a simple quantizer structure, where each product codebook is symmetric with respect to the diagonal line in the underlying vector space. It is known that 1-SAPQ shows a good performance for i.i.d. sources. In this paper, a study on designing 1-SAPQ for the first-order Markov process. For an efficient design of 1-SAPQ, an algorithm for the initial codebook is proposed, and through the numerical analysis it is shown that 1-SAPQ shows better quantizer distortion than the VQ case, of which encoding complexity is similar to that of 1-SAPQ, and shows distortions, which are close to that of the DPCM(differential pulse coded modulation) scheme with the Lloyd-Max quantizer.

• Journal of the Institute of Electronics Engineers of Korea SP
• /
• v.43 no.4 s.310
• /
• pp.46-54
• /
• 2006

Recently, the important of a personal identification is increasing according to expansion using each on-line commercial transaction and personal ID-card. Although a personal ID-card embedded RFID(Radio Frequency Identification) tag is gradually increased, the way for a person's identification is deficiency. So we need automatic methods. Because RFID tag is vary small storage capacity of memory, it needs effective feature extraction method to store personal biometrics information. We need new recognition method to compare each feature. In this paper, we studied the face verification system using Hippocampal neuron modeling algorithm which can remodel the hippocampal neuron as a principle of a man's brain in engineering, then it can learn the feature vector of the face images very fast. and construct the optimized feature each image. The system is composed of two parts mainly. One is feature extraction using NMF(Non-negative Matrix Factorization) and LDA(Linear Discriminants Analysis) mixture algorithm and the other is hippocampal neuron modeling and recognition simulation experiments confirm the each recognition rate, that are face changes, pose changes and low-level quality image. The results of experiments, we can compare a feature extraction and learning method proposed in this paper of any other methods, and we can confirm that the proposed method is superior to the existing method.

• Journal of the Institute of Electronics Engineers of Korea CI
• /
• v.41 no.1
• /
• pp.9-18
• /
• 2004

This paper presents an efficient image compression method for memory reduction in multimedia processor which can be simply implemented in hardware and provides high performance. The multimedia processor, which includes processing of high-resolution images and videos, requires large memories: they are external frame memories to store frames and internal line memories for implementing some linear filters. If we can reduce those memories by adopting a simple compression method in multimedia processor, it will strengthen its cost competitiveness. There exist many standards for efficiently compressing images and videos. However, those standards are too complex for our purpose and most of them are 2-D block-based methods, which do not support raster scanned input and output. In this paper, we propose a low-complexity compression method which has good performance, can be implemented with simple hardware logic, and supports raster scan. We have adopted 1${\times}$8 Hadamard transform for simple implementation in hardware and compression efficiency. After analyzing the coefficients, we applied an adaptive thresholding and quantization. We provide some simulation results to analyze its performance and compare with the existing methods. We also provide its hardware implementation results and discuss about cost reduction effects when applied in implementing a multimedia processor.