• Title/Summary/Keyword: junction structure

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Large Tunneling Magnetoresistance of a Ramp-type Junction with a SrTiO3 Tunneling Barrier

  • Lee, Sang-Suk;Yoon, Moon-Sung;Hwang, Do-Guwn;Rhie, Kung-Won
    • Journal of Magnetics
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    • v.8 no.2
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    • pp.89-92
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    • 2003
  • The tunneling magnetoresistance (TMR) of a ramp-edge type junction with SrTiO$_3$barrier layer has been stud-ied. The samples with a structure of glass/NiO(600${\AA}$)/Co(100${\AA}$)/SrTiO$_3$(400 ${\AA}$)/SrTiO$_3$(20-100${\AA}$)/NiFe(100${\AA}$) were prepared by the sputtering and etched by the electron cyclotron (ECR) argon ion milling. Nonlinear I-V characteristics were obtained from a ramp-type tunneling junctions, having the dominant difference between two different external magnetic fields (${\pm}$100 Oe) perpendicular to the junction edge line. In the SrTiO$_3$ barrier thickness of 40${\AA}$, the TMR was 52.7% at a bias voltage of -50 mV The bias voltage dependence of resistance and TMR in a ramp-type tunneling junction was similar with those of the layered TMR junction.

Properties of Recessed Polysilicon/Silicon($n^{+}$) - Silicon(P) Junction with Process Condition (공정조건에 따른 함몰된 다결정실리콘/실리콘($n^{+}$) - 실리콘(p) 접합의 특성)

  • 이종호;최우성;박춘배;이종덕
    • Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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    • 1994.05a
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    • pp.152-153
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    • 1994
  • A recessed $n^{+}$-p junction diode with the serf-aligned structure is proposed and fabricated by using the polysilicon as an $n^{+}$ diffusion source. The diode structure can be applicable to the emitter-base formation of high performance bipolar device and the $n^{+}$ polysilicon emitter has an important effect on the device characteristics. The considered parameters for the polysilicon formation are the deposition condition $As^{+}$ dose for the doping of the polysilicon, and the annealing using RTP system. The vertical depth profiles of the fabricated diode are obtained by SIMS. The eleotrical characteristics are analyzed in trims of the ideality factor of diode (n), contact resistance arid reverse leakage current. The $As_{+}$ dose for the formation of good junction is current. The $As^{+}$ dose for the formation of goodjunctions is about 1∼2${\times}$$10^{16}$$cm^{-2}$ at given RTA condition ($1100^{\circ}C$, 10 sec). The $n^{+}$-p structure is successfully applied to the self-aligned bipolar device adopting a single polysilicon technology.

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Mechanism for Gating of Gap Junction Channel. (간극결합채널의 개폐기전)

  • 오승훈
    • Journal of Life Science
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    • v.14 no.5
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    • pp.882-890
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    • 2004
  • Gap junction is a membrane structure facilitating the direct transmission of several ions and small molecules between two cells. It is also called an 'intercellular channel' to distinguish it from other well-known cellular channels (e.g. sodium and potassium channels). Gap junction channels are not passive conduits, rather the ion channels modulated by several stimuli including pH, calcium ion, voltage, and a chemical modification (mainly known as phosphorylation). Among them, the effects of voltage on the gating of gap junction channels have been well studied. Gap junction channels are more sensitive to the transjunctional potential ($V_j$) between two cells rather than the membrane potential($V_m$) between inside and outside the cell. In this review, I will summarize the general properties of gap junction channel and discuss the gating mechanism for the gap channels.

A Study on the Electrical Characteristics according to Growth of Trench SiO2 Inside Super Junction IGBT Pillar (Super Junction IGBT 필러 내부 Trench SiO2성장에 따른 전기적 특성에 관한 연구)

  • Lee, Geon Hee;Ahn, Byoung Sup;Kang, Ey Goo
    • Journal of IKEEE
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    • v.25 no.2
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    • pp.344-349
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    • 2021
  • This paper proposes a structure in which Trench SiO2 is grown inside of Super Junction IGBT P-Pillar. When observing the electric field in 3D, we checked the region where the electric field have not affected inside of the P-Pillar. The pillar region's portion resistance is varied by the breakdown voltage and size of each pillar, which reduces the size by growing SiO2 after trenching has no field effect inside of that. At 4.5kV the same breakdown voltage, it was confirmed that the On-state voltage drop improved by about 58%, 19% compared to Field Stop IGBT and conventional Super Junction IGBT.

Thin Film Amorphous/Bulk Crystalline Silicon Tandem Solar Cells with Doped nc-Si:H Tunneling Junction Layers

  • Lee, Seon-Hwa;Lee, Jun-Sin;Jeong, Chae-Hwan
    • Proceedings of the Korean Vacuum Society Conference
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    • 2015.08a
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    • pp.257.2-257.2
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    • 2015
  • In this paper, we report on the 10.33% efficient thin film/bulk tandem solar cells with the top cell made of amorphous silicon thin film and p-type bulk crystalline silicon bottom cell. The tunneling junction layers were used the doped nanocrystalline Si layers. It has to allow an ohmic and low resistive connection. For player and n-layer, crystalline volume fraction is ~86%, ~88% and dark conductivity is $3.28{\times}10-2S/cm$, $3.03{\times}10-1S/cm$, respectively. Optimization of the tunneling junction results in fill factor of 66.16 % and open circuit voltage of 1.39 V. The open circuit voltage was closed to the sum of those of the sub-cells. This tandem structure could enable the effective development of a new concept of high-efficiency and low cost cells.

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Investigation of Junction-less Tunneling Field Effect Transistor (JL-TFET) with Floating Gate

  • Ali, Asif;Seo, Dongsun;Cho, Il Hwan
    • JSTS:Journal of Semiconductor Technology and Science
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    • v.17 no.1
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    • pp.156-161
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    • 2017
  • This work presents a novel structure for junction-less tunneling field effect transistor (JL-TFET) with a floating gate over the source region. Introduction of floating gate instead of fixed metal gate removes the limitation of fabrication process suitability. The proposed device is based on a heavily n-type-doped Si-channel junction-less field effect transistor (JLFET). A floating gate over source region and a control-gate with optimized metal work-function over channel region is used to make device work like a tunnel field effect transistor (TFET). The proposed device has exhibited excellent ID-VGS characteristics, ION/IOFF ratio, a point subthreshold slope (SS), and average SS for optimized device parameters. Electron charge stored in floating gate, isolation oxide layer and body doping concentration are optimized. The proposed JL-TFET can be a promising candidate for switching performances.

Fabrication of Vertical Organic Junction Transistor by Direct Printing Method

  • Shin, Gunchul;Kim, Gyu-Tae;Ha, Jeong Sook
    • Bulletin of the Korean Chemical Society
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    • v.35 no.3
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    • pp.731-736
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    • 2014
  • An organic junction transistor with a vertical structure based on an active layer of poly(3-hexylthiophene) was fabricated by facile micro-contact printing combined with the Langmuir-Schaefer technique, without conventional e-beam or photo-lithography. Direct printing and subsequent annealing of Au-nanoparticles provided control over the thickness of the Au electrode and hence control of the electrical contact between the Au electrode and the active layer, ohmic or Schottky. The junction showed similar current-voltage characteristics to an NPN-type transistor. Current through the emitter was simply controllable by the base voltage and a high transconductance of ~0.2 mS was obtained. This novel fabrication method can be applied to amplifying or fast switching organic devices.

Investigation of Curvature Effect on Planar InP/InGaAs Avalanche Photodiodes for Edge Breakdown Suppression (경계항복 억제를 위한 평판형 InP/InGaAs 애벌랜치 포토다이오드의 곡률 효과 분석)

  • 이봉용;정지훈;윤일구
    • Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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    • 2002.07a
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    • pp.206-209
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    • 2002
  • With the progress of semiconductor processing technology, avalanohe photodiodes (APDs) based on InP/InGaAs are used for high-speed optical receiver modules. Planar-type APDs give higher reliability than mesa-type APDs. However, Planar-type APDs are struggled with a problem of intensed electric field at the junction curvature, which causes edge breakdown phenomena at the junction periphery. In this paper, we focused on studying the effects of junction curvature for APDs performances by different etching processes followed by single diffusion to from p-n junction. The performance of each process is characterized by observing electric field profiles and carrier generation rates. From the results, it can be understood to predict the optimum structure, which can minimize edge breakdown and improve the manufacturability.

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3.3kV Low Resistance 4H-SiC Semi-SJ MOSFET (3.3kV급 저저항 4H-SiC Semi-SJ MOSFET)

  • Cheon, Jin-Hee;Kim, Kwang-Soo
    • Journal of IKEEE
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    • v.23 no.3
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    • pp.832-838
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    • 2019
  • In this paper, 4H-SiC MOSFET, the next generation power semiconductor device, was studied. In particular, Semi-SJ MOSFET structures with improved electrical characteristics than conventional DMOSFET structures were proposed in the class of 3300V, and static characteristics of conventional and proposed structures were compared and analyzed through TCAD simulations. Semi-SuperJunction MOSFET structure is partly structure that introduces SuperJunction, improves Electric field distribution through the two-dimensional depletion effect, and increases breakdown voltage. Benefit from the improvement of breakdown voltage, which can improve the on resistance as high doping is possible. The proposed structure has a slight reduction in breakdown voltage, but has an 80% decrease in on resistance compared to the conventional DMOSFET structure, and a 44% decrease in on resistance compared to the Current Spreading Layer(CSL) structure that improves the conventional DMOSFET structure.

The Study of Ni-Pd Alloy Characteristics to Form a NiSi for Shallow S/D Junction (Shallow S/D Junction에 적용 가능한 NiSi를 형성하기 위한 Ni-Pd 합금의 특성 연구)

  • Lee, Won-Jae;Oh, Soon-Young;Agchbayar, Tuya;Yun, Jang-Gn;Kim, Yong-Jin;Zhang, Ying-Ying;Zhong, Zhun;Kim, Do-Woo;Cha, Han-Seob;Heo, Sang-Bum;Wang, Jin-Suk;Lee, Hi-Deok
    • Proceedings of the IEEK Conference
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    • 2005.11a
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    • pp.603-606
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    • 2005
  • In this paper, the formation and thermal stability of Ni-silicide using Ni-Pd alloys is studied for ultra shallow S/D junction of nano-scale CMOSFETs. There are no different effects when Ni-Pd is used in single structure and TiN capping structure. But, in case of Cobalt interlayer structure, it was found that Pure Ni had lower sheet resistance than Ni-Pd, because of a thick silicide. Also, Ni-Pd has merits that surface of silicide and interface between silicide and silicon have a good morphology characteristics. As a result, Ni-Pd is an optimal candidate for shallow S/D junction when cobalt is used for thermal stability.

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