• International Journal of Precision Engineering and Manufacturing
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• v.7 no.4
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• pp.8-13
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• 2006

Nanoscale fabrication of silicon substrate in an aqueous solution based on the use of atomic force microscopy was demonstrated. A specially designed cantilever with a diamond tip, allowing the formation of a mask layer on the silicon substrate by a simple scratching process (Tribo-Nanolithography, TNL), has been applied instead of the conventional silicon cantilever for scanning. A slant nanostructure can be fabricated by a process in which a thin mask layer rapidly forms on the substrate at the diamond tip-sample junction along scanning path of the tip, and simultaneously, the area uncovered with the mask layer is etched. This study demonstrates how the TNL parameters can affect the formation of the mask layer and the shape of 3-D structure, hence introducing a new process of AFM-based nanolithography in aqueous solution.

• Progress in Superconductivity
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• v.9 no.2
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• pp.157-161
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• 2008

Due to high speed operations and ultra low power consumptions RSFQ logic circuit is a very good candidate for future electronic device. The focus of the RSFQ circuit development has been on the advancement of analog-to-digital converters and microprocessors. Recent works on RSFQ ALU development showed the successful operation of an 1-bit block of ALU at 40 GHz. Recently, the study of an RSFQ analog-to-digital converter has been extended to the development of a single chip RF digital receiver. Compared to the voltage logic circuits, RSFQ circuits operate based on the pulse logic. This naturally leads the circuit structure of RSFQ circuit to be pipelined. Delay time on each pipelined stage determines the ultimate operating speed of the circuit. In simulations, a two junction Josephson transmission line's delay time was about 10 ps, a splitter's 14.5 ps, a switch's 13 ps, a half adder's 67 ps. Optimization of the 4-bit ALU circuit has been made with delay time consideration to operate comfortably at 10 GHz or above.

• Proceedings of the Korean Vacuum Society Conference
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• 2012.02a
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• pp.306-306
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• 2012

본 연구에서는 태양전지 소자의 온도에 따른 전류-전압(I-V) 특성 변화를 통해 태양전지 다이오드의 전기적 특성을 분석하였다. 상온 조건의 경우 공핍층 영역(SCR)과 준중성 영역(QNR)에서 각각 3.02와 1.76의 이상 계수 값을 보였으며, 온도가 300 K에서 500 K으로 상승함에 따라 SCR 영역에서는 감소하는 경향을, QNR 영역에서는 증가하는 경향을 보였다. 이는 온도 상승에 따른 공핍층 영역에서의 캐리어 흐름 증가와 대면적 공정 과정에서의 오염물 침투 및 dangling bond 등의 결함으로 인한 bulk 에서의 캐리어 재결합에 따른 것으로 판단된다. 또한 텍스처링 공정에 따른 태양전지 소자의 접합면 균일성 확인을 위한 I-V 측정 결과 SCR 영역에서는 40.87%의 평균 전류 분산을, QNR 영역에서는 10.59%의 평균 전류 분산을 보였다. 이는 텍스처링 공정으로 형성된 접합면에서의 피라미드 구조가 원인이 되는 것으로 판단되며, 전체 다이오드 전류 흐름에 영향을 주게 된다. 이러한 공정 과정에서의 결함 및 접합 구조로 인해 태양전지 다이오드는 일반 다이오드에 비해 비이상적인 전기적 특성을 보이게 된다.

• Journal of Korea Society of Industrial Information Systems
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• v.8 no.1
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• pp.9-17
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• 2003

The finite-difference time-domain (FDTD) method is used to analyze circular waveguide transformer in order to match different two waveguides. 2-dimensional cylindrical FDTD algorithm is applied for rotationally symmetric. The transformer is inserted at a circular-to-circular waveguide junction and two type transformers are proposed. One is a partially dielectric filled circular waveguide type and the other is filled a tapered circular dielectric rod. The numerical results are derived for various structure parameters, such as transformer length. dielectric diameter and waveguide diameter.

• 한국정보디스플레이학회:학술대회논문집
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• 2005.07a
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• pp.342-344
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• 2005

We have simulated a symmetric dual-gate TFT which has triple floating n+ channel to improve the on-current of the dual-gate TFT. We achieved a low hole concentration at the source and channel junction causes the improvement the potential barrier so that we observed the reduction of the kink-effect. In this paper, we observed the reduction of the kink-effect compared with the conventional single-gate TFT and the improvement of the on-current compared with the conventional dual-gate TFT.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.17 no.2
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• pp.196-200
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• 2004

Using polyimide Langmuir-Blodgett(LB) films as a tunneling harrier, we fabricated Au/Polyimide/1-layer arachidic acid/Pb structure in order to investigate electron transport properties through a junction. It was found that 9-layer polyimide LB films function as a good tunneling harrier in a study of current-voltage(I-V) chararteristics. And several peaks originating in the vibrational modes of the constituent molecules of 1-layer arachidic acid LB films were clearly observed in d$^2$V/dI$^2$- V corves.

• ETRI Journal
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• v.28 no.3
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• pp.401-404
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• 2006

A new log-domain first-order multifunction filter is proposed in this letter. The proposed filter is systematically derived using the state-space synthesis procedure from a corresponding block diagram. It provides low-pass (LP), high-pass (HP), and all-pass (AP) responses simultaneously for a single input signal. The filter circuit has a very simple structure since it uses only bipolar junction transistors (BJTs) and a grounded capacitor. It can be electronically tuned by changing an external current. The filter has a greater bandwidth due to its inherent current-mode and log-domain operations. PSPICE simulations are given to confirm the theoretical analysis.

• The Transactions of the Korean Institute of Electrical Engineers
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• v.45 no.2
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• pp.230-234
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• 1996

A new trenched Hybrid Schottky INjection Field Effect Transistor (HSINFET) is proposed and verified by 2-D semiconductor device simulation. The feature of the proposed structure is that the hybrid Schottky injector is implemented at the trench sidewall and p-n junction injector at the upper sidewall and bottom of a trench. Two-dimensional simulation has been performed to compare the new HSINFET with the SINFET, conventional HSINFET and lateral insulated gate bipolar transistor(LIGBT). The numerical results shows that the current handling capability of the proposed HSINFET is significantly increased without sacrificing turn-off characteristics. The proposed HSINFET exhibits higher latch-up current density and much faster switching speed than the lateral IGBT. The forward voltage drop of the proposed HSINFET is 0.4 V lower than that of the conventional HSINFET and the turn-off time of the trenched HSINFET is much smaller than that of LIGBT.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2000.11a
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• pp.17-20
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• 2000

This study is about a retrograde triple well employed in the Cell tr. of next DRAM and flash memory. Triple well structure is formed deep n-well under the light p-well using MeV ion implantation. MeV P implanted deep n-well was observed to show greatly improved characteristics of electrical isolation and soft error. Junction leakage current, however, showed a critical behavior as a function of implantation and annealing conditions. {311} defects were observed to be responsible for the leakage current. {311} defects were generated near the R$\_$p/ (Projected range) region and grown upward to the surface during annealing. This is study on the defect behavior in device region as a function of implantation and annealing conditions.

• Proceedings of the KIEE Conference
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• 2009.04b
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• pp.125-130
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• 2009

This paper reviews the characteristics technical trends in Power MOSFET technology that are leading to improvements in power loss for power electronic system. The power electronic technology requires the marriage of power device technology with MOS-gated device and bipolar analog circuits. The technology challenges involved in combining power handling capability with finger gate, trench array, super junction structure, and SiC transistor are described, together with examples of solutions for telecommunications, motor control, and switch mode power supplies.