• 대한전기학회:학술대회논문집
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• 대한전기학회 1995년도 하계학술대회 논문집 C
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• pp.1085-1087
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• 1995

A large leakage current may be one of the critical issues for poly-silicon thin film transistors(poly-Si TFTs) for LCD applications. In order to reduce the leakage current of poly-Si TFTs, several offset gated structures have been reported. However, those devices, where the offset length in the source region is not same as that in the drain region, exhibit the asymmetric electrical performances such as the threshold voltage shift and the variation of the subthreshold slope. The different offset length is caused by the additional mask step for the conventional offset structures. Also the self-aligned implantation may not be applicable due to the mis-alignment problem. In this paper, we propose a new fabrication method for poly-Si TFTs with a self-aligned offset gated structure by employing a photo resistor reflow process. Compared with the conventional poly-Si TFTs, the device is consist of two gate electrodes, of which one is the entitled main gate where the gate bias is employed and the other is the entitled subgate which is separate from both sides of the main gate. The poly-Si channel layer below the offset oxide is protected from the injected ion impurities for the source/drain implantation and acts as an offset region of the proposed device. The key feature of our new device is the offset lesion due to the offset oxide. Our experimental results show that the offset region, due to the photo resistor reflow process, has been successfully obtained in order to fabricate the offset gated poly-Si TFTs. The advantages of the proposed device are that the offset length in the source region is the same as that in the drain region because of the self-aligned implantation and the proposed device does not require any additional mask process step.

• 전자공학회논문지A
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• 제29A권10호
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• pp.29-34
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• 1992

JFET's with gate lengths ranging from 1$\mu$m to 8.3$\mu$m are successfully fabricated on InP substrate where the long haul (1.3$\mu$m~8.3$\mu$m) OEIC's(OptoElectronic Integrated Circuits) have been made. The pn junction of InP JFET's is made by co-implantation and RTA process. JFET's have etched-mesa-gate structure and the maximum gm larger than 90mS/mm was measured and this is the highest record in JFET's of such structure without S/D n$^{+}$ ion implantation. To maintain maximum g$_m$ should be well controlled the overetch of n-layer which inevitably occurs during etching off the unused p-layer. The I-V characteristic is checked during p-layer etch, for this purpose. A dc voltage gain of 11 is obtained from a preamplifier circuit thus fabricated.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2002년도 하계종합학술대회 논문집(2)
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• pp.29-32
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• 2002

This paper describes a novel structure of NMOSFET with elevated SiGe source/drain region and ultra-shallow source/drain extension(SDE)region. A new ultra-shallow junction formation technology. Which is based on damage-free process for rcplacing of low energy ion implantation, is realized using ultra-high vacuum chemical vapor deposition(UHVCVD) and excimer laser annealing(ELA).

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2002년도 하계종합학술대회 논문집(2)
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• pp.365-368
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• 2002

WSW(Wrap Side Wall) is proposed to decrease junction electric field in this paper. WSW process is fabricated after first gate etch, followed NMI ion implantation and deposition & etch nitride layer New WSW structure has buffer layer to decrease electric field. Also we compared the hot carrier characteristics of WSW and conventional. Also, we design a test pattern including pulse generator, level shifter and frequency divider, so that we can evaluate AC hot carrier degradation on-chip.

• 반도체디스플레이기술학회지
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• 제16권4호
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• pp.20-24
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• 2017

Currently, techniques mainly used in semiconductor impurity diffusion processes include furnace thermal diffusion, ion implantation, and vacuum plasma doping. However, there is a disadvantage that the process equipment and the unit cost are expensive. In this study, boron diffusion process using relatively inexpensive atmospheric plasma was conducted to solve this problem. With controlling parameters of Boron diffusion process, the doping characteristics were analyzed by using secondary ion mass spectrometry. As a result, the influence of each variable in the doping process was analyzed and the feasibility of atmospheric plasma doping was confirmed.

• 한국정보통신학회:학술대회논문집
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• 한국해양정보통신학회 2002년도 춘계종합학술대회
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• pp.279-282
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• 2002

In this paper, we discuss influence of process condition on contact resistance in WSix deposition process. In the WSix deposition process, we confirmed that word line to bit line contact resistance(WBCR) due to temperature of word line WSix deposition among various process condition split experiment. RTP treatment, d-poly ion implantation dose and thickness was estimated a little bit influence on contact resistance. Also, life time of shower head in the process chamber for WSix deposition related to contact resistance. The results obtained in this study are applicable to process control and electrical characteristics for high reliability and high density DRAM's.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2005년도 추계학술대회 논문집 Vol.18
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• pp.49-50
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• 2005

Nitrogen and phosphorus ions were implanted into ZnO thin film fabricated by pulsed laser deposition. ion implanted ZnO thin films were annealed from $700^{\circ}C$ to $1000^{\circ}C$ using rapid thermal annealing process. The electron concentration was changed form $10^{20}$ to $10^{18}/cm^3$. Effect of nitrogen and phosphorus in ZnO thin films was certified and the structural and optical properties of nitrogen and phosphorus doped ZnO thin films depending on concentration of nitrogen and phosphorus were investigated.

• The Journal of Advanced Prosthodontics
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• 제6권3호
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• pp.157-164
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• 2014

PURPOSE. This study focused on in vitro cell differentiation and surface characteristics in a magnesium coated titanium surface implanted on using a plasma ion source. MATERIALS AND METHODS. 40 commercially made pure titanium discs were prepared to produce Ti oxide machined surface (M) and Mg-incorporated Ti oxide machined surface (MM). Surface properties were analyzed using a scanning electron microscopy (SEM). On each surface, alkaline phosphatase (ALP) activity, alizarin red S staining for mineralization of MC3T3-E1 cells, and quantitative analysis of osteoblastic gene expression, were evaluated. Actin ring formation assay and gene expression analysis of TRAP and GAPDH performing RT-PCR were performed to characterize osteoclast differentiation on mouse bone marrow-derived macrophages (BMMs). RESULTS. MM showed similar surface morphology and surface roughness with M, but was slightly smoother after ion implantation at the micron scale. M was more hydrophobic than MM. No significant difference between surfaces on ALP activity at 7 and 14 days were observed. Real-time PCR analyses showed similar levels of mRNA expression of the osteoblast phenotype genes; osteopontin (OPN), osteocalcin (OCN), bone sialoprotein (BSP), and collagen 1 (Col 1) in cell grown on MM at 7, 14 and 21 days. Alizarin red S staining at 21 days showed no significant difference. BMMs differentiation increased in M and MM. Actin ring formation assay and gene expression analysis of TRAP showed osteoclast differentiation to be more active on MM. CONCLUSION. Both M and MM have a good effect on osteoblastic cell differentiation, but MM may speed the bone remodeling process by activating on osteoclast differentiation.

• 한국재료학회지
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• 제10권12호
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• pp.812-818
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• 2000

본 연구에서는 Ge PAM이 선폭 미세화에 따른 C54 실리사이드화 및 실제 CMOS 트랜지스터 접합부에서의 각종 전기적 특성에 미치는 영향을, As PAM과의 비교를 통하여 관찰하였다. 평판 상에서 각 PAM 및 기판의 도핑 상태에 따른 Rs의 변화량을 측정하였으며, 각 PAM 방식은 기존의 살리사이드 TiSi$_2$에 비해 개선된 C54 형성 효과를 보였다. 특히, Ge PAM은 n+ 기판에서 As PAM보다 효과적인 실리사이드화를 보였고, 이 경우 XRB 상에서도 가장 강한 (040) C54 배향성을 나타내었다. ~0.25$\mu\textrm{m}$ 선폭 및 n+ 접합층에서 기존 방식에 비해 As과 Ge PAM은 각각 ~85,66%의 개선된 바저항을 보였으며, P+ 접합층에서는 As과 Ge PAM 모두 62~63% 정도의 유사한 Rs 개선 효과를 보였다. 콘택 저항에서도 각 콘택 크기 별로 바저항(bar resistance) 개선과 같은 경향의 PAM 효과를 관찰하였으며, 모든 경우 10 $\Omega$/ct. 이하로 양호한 결과를 보였다. 누설 전류는 area 형 패턴에서는 모든 공정 조건에서 <10E-14A/$\mu\textrm{m}^{2}$ 이하로, edge 형에서는 특히 P+ 접합부에서 As 또는 Ge PAM 적용 시 <10E-13 A/$\mu\textrm{m}^{2}$ 이하로 다소 누설 전류를 안정화시키는 결과를 보였다. 이러한 결과는 XTEM에 의해 관찰된 바 Ge PAM 적용 시 기존의 경우에 (PAM 적용 안한 경우) 비해 유사한 평활도의 TiSi$_2$박막 형상과 일치하였으며, 또한 본 실험의 Ge PAM 이온주입 조건이 접합층에 손상을 주지 않는 범위에서 적정화되었음을 제시하였다

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2003년도 하계종합학술대회 논문집 II
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• pp.731-734
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• 2003

An atomistic process modeling, Kinetic Monte Carlo simulation, has the advantage of being both conceptually simple and extremely powerful. Instead of diffusion equations, it is based on the definitions of the interactions between individual atoms and defects. Those interactions can be derived either directly from molecular dynamics, first principles calculations, or from experiment. In this paper, as a simple illustration of the kinetic Monte Carlo we simulate defects (self-interstitials and vacancies) diffusion after ion implantation in Si crystalline.