• Title/Summary/Keyword: input delay

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Design of an iterative learning controller for a class of linear dynamic systems with time-delay (시간 지연이 있는 선형 시스템에 대한 반복 학습 제어기의 설계)

  • Park, Kwang-Hyun;Bien, Zeung-Nam;Hwang, Dong-Hwan
    • Journal of Institute of Control, Robotics and Systems
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    • v.4 no.3
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    • pp.295-300
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    • 1998
  • In this paper, we point out the possibility of the divergence of control input caused by the estimation error of delay-time when general iterative learning algorithms are applied to a class of linear dynamic systems with time-delay in which delay-time is not exactly measurable, and then propose a new type of iterative learning algorithm in order to solve this problem. To resolve the uncertainty of delay-time, we propose an algorithm using holding mechanism which has been used in digital control system and/or discrete-time control system. The control input is held as constant value during the time interval of which size is that of the delay-time uncertainty. The output of the system tracks a given desired trajectory at discrete points which are spaced auording to the size of uncertainty of delay-time with the robust property for estimation error of delay-time. Several numerical examples are given to illustrate the effeciency of the proposed algorithm.

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Time-Delay Effects on DC Characteristics of Peak Current Controlled Power LED Drivers

  • Kim, Marn-Go;Jung, Young-Seok
    • Proceedings of the KIPE Conference
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    • 2011.07a
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    • pp.481-482
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    • 2011
  • New discrete time domain models for the peak current controlled (PCC) power LED drivers in continuous conduction mode include for the first time the effects of time delay in the pulse-width-modulator. Realistic amounts of time delay are found to have significant effects on the average output LED current and on the critical inductor value at the boundary between two conduction modes. Especially, the time delay can provide an accurate LED current for the PCC buck converter with a wide input voltage. The models can also predict the critical inductor values at the mode boundary as functions of the input voltage and the time delay.

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Delay-dependent Robust $H_{\infty}$ Control for Uncertain Discrete-time Descriptor Systems with Interval Time-varying Delays in State and Control Input (상태와 입력에 구간 시변 시간지연을 가지는 불확실 이산시간 특이시스템의 지연 종속 강인 $H_{\infty}$ 제어)

  • Kim, Jong-Hae
    • The Transactions of The Korean Institute of Electrical Engineers
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    • v.58 no.1
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    • pp.193-198
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    • 2009
  • In this paper, we consider the design problem of delay-dependent robust $H{\infty}$ controller of discrete-time descriptor systems with parameter uncertainties and interval time-varying delays in state and control input by delay-dependent LMI (linear matrix inequality) technique. A new delay-dependent bounded real lemma for discrete-time descriptor systems with time-varying delays is derived. The condition for the existence of robust $H{\infty}$ controller and the robust $H{\infty}$ state feedback control law are proposed by LMI approach. A numerical example is demonstrated to show the validity of the design method.

Low Delay IntMDCT Using Power Complementary Window (파워 상호보완 윈도우를 이용한 지연 감소 IntMDCT)

  • Lee, Sang-Hwan;Lee, In-Sung
    • The Journal of the Acoustical Society of Korea
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    • v.32 no.6
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    • pp.525-531
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    • 2013
  • In this paper, we propose to apply low delay algorithm using power complementary window to Integer Modified Discrete Cosine Transform (IntMDCT). Conventional transform, the Modified Discrete Cosine Transform (MDCT) usually produces floating point values for integer input values. This causes the expansion of the data. To refine on this, IntMDCT that produces integer values even for integer input values have emerged. However, IntMDCT has a problem of the algorithm delay, such as MDCT. Delay has became a key issue in environments for the purpose of real-time communications. In order to reduce the delay, the proposed algorithm was applied and the results of the performance evaluation show that delay of IntMDCT has reduced by halfexisting delay.

An Analytical Switching-Dependent Timing Model for Multi-Coupled VLSI Interconnect lines (디커플링 방법을 이용한 RC-Coupled 배선의 해석적 지연시간 예측 모델)

  • Kim, Hyun-Sik;Eo, Yung-Seon;Shim, Jong-In
    • Proceedings of the IEEK Conference
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    • 2004.06b
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    • pp.439-442
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    • 2004
  • Timing delays due to VLSI circuit interconnects strongly depend on neighbor line switching patterns as well as input transition time. Considering both the input transition and input switching pattern, a new analytical timing delay model is developed by using the decoupling technique of transfer multi-coupled lines into an effective single line. The analytical timing delay model can determine the timing delay of multi-coupled lines accurately as well as rapidly. It is verified by using DSM-Technology ($0.1{\mu}m$ /low-k copper-based process) that the model has excellent agreement with the results of SPICE simulation.

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Rate Proportional SCFQ Algorithm for High-Speed Packet-Switched Networks

  • Choi, Byung-Hwan;Park, Hong-Shik
    • ETRI Journal
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    • v.22 no.3
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    • pp.1-9
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    • 2000
  • Self-Clocked Fair Queueing (SCFQ) algorithm has been considered as an attractive packet scheduling algorithm because of its implementation simplicity, but it has unbounded delay property in some input traffic conditions. In this paper, we propose a Rate Proportional SCFQ (RP-SCFQ) algorithm which is a rate proportional version of SCFQ. If any fair queueing algorithm can be categorized into the rate proportional class and input is constrained by a leaky bucket, its delay is bounded and the same as that of Weighted Fair Queueing (WFQ) which is known as an optimal fair queueing algorithm. RP-SCFQ calculates the timestamps of packets arriving during the transmission of a packet using the current value of system potential updated at every packet departing instant and uses a starting potential when it updates the system potential. By doing so, RP-SCFQ can have the rate proportional property. RP-SCFQ is appropriate for high-speed packet-switched networks since its implementation complexity is low while it guarantees the bounded delay even in the worst-case input traffic conditions.

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Stabilization of Input-Delayed TS Fuzzy Systems

  • Lee, Ho-Jae;Park, Jin-Bae;Cha, Dae-Beum;Joo, Young-Hoon
    • Proceedings of the Korean Institute of Intelligent Systems Conference
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    • 2001.05a
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    • pp.140-143
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    • 2001
  • In this paper, a control problem of the Takagi-Sugeno(TS) fuzzy system with time-varying input delay is considered. It is well known that the delay is one of the major sources responsible for the instability of the controlled system. A systematic design technique is developed based on the Lyapunov-Razumikhin stability theorem. A sufficient condition for the global asymptotic stability of the TS fuzzy systems is formulated in terms of linear matrix inequalities (LMIs). The derived condition can deal with any time-varying input delay within the admissible bound. The effectiveness of the proposed controller design technique is demonstrated by a numerical simulation.

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A study on the Hankel approximation of input delay systems (입력 시간지연 시스템의 한켈 근사화에 관한 연구)

  • Hwang, Lee-Cheol;Ha, Hui-Gwon;Lee, Man-Hyeong
    • Journal of Institute of Control, Robotics and Systems
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    • v.4 no.3
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    • pp.308-314
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    • 1998
  • This paper studies the problem of computing the Hankel singular values and vectors in the input delay systems. It is shown that the Hankel singular values are solutions to a transcendental equation and the Hankel singular vectors are obtained from the kernel of the matrix. The computation is carried out in state space framework. Finally, Hankel approximation of a simple example shows the usefulness of this study.

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On a Logical Path Design for Optimizing Power-delay under a Fixed-delay Constraint (고정 지연 조건에서 전력-지연 효율성의 최적화를 위한 논리 경로 설계)

  • Lee, Seung-Ho;Chang, Jong-Kwon
    • The KIPS Transactions:PartA
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    • v.17A no.1
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    • pp.27-32
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    • 2010
  • Logical Effort is a simple hand-calculated method that measures quick delay estimation. It has the advantage of reducing the design cycle time. However, it has shortcomings in designing a path for minimum area or power under a fixed-delay constraint. In this paper, we propose an equal delay model and, based on this, a method of optimizing power-delay efficiency in a logical path. We simulate three designs of an eight-input AND gate using our technique. Our results show about 40% greater efficiency in power dissipation than those of Logical Effort method.

Time Discretization of the Nonlinear System with Variable Time-delayed Input using a Taylor Series Expansion

  • Choi, Hyung-Jo;Chong, Kil-To
    • 제어로봇시스템학회:학술대회논문집
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    • 2005.06a
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    • pp.2562-2567
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    • 2005
  • This paper suggests a new method discretization of nonlinear system using Taylor series expansion and zero-order hold assumption. This method is applied into the sampled-data representation of a nonlinear system with input time delay. Additionally, the delayed input is time varying and its amplitude is bounded. The maximum time-delayed input is assumed to be two sampling periods. Them mathematical expressions of the discretization method are presented and the ability of the algorithm is tested for some of the examples. And 'hybrid' discretization scheme that result from a combination of the ‘scaling and squaring' technique with the Taylor method are also proposed, especially under condition of very low sampling rates. The computer simulation proves the proposed algorithm discretized the nonlinear system with the variable time-delayed input accurately.

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