• Journal of Institute of Control, Robotics and Systems
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• v.17 no.2
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• pp.171-175
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• 2011

In this paper, I have developed a high-speed and high-resolution measuring device in order to check the performance of drycell. The system is developed for the drycell manufacturing plant. Measuring time is one of key factors to inference on the production speed. So the developed system is designed to generate the classified result up to 1200ea/min. In the other words, each product can be classified within 25ms. There have been many studies to estimate both state of charge as well as state of health, such as OCV (Open Circuit Voltage), SC (Short Circuit) and measuring impedance with frequency pulse. But those methods take a few second due to surface discharge. To overcome the phenomenon, I developed the method to engage the reverse current to two electrodes of battery. As a result, I could achieve to measure the indigenous capacity without the problem of surface discharge.

• Proceedings of the IEEK Conference
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• 1998.06a
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• pp.875-878
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• 1998

In this thesis, we present efficient techniques to reduce the switching activity in a CMOS combinational logic network based on local logic transforms. But this techniques is not appropriate in the view of testability because of deteriorating the random pattern testability of a circuit. This thesis proposes a circuit design method having two operation modes. For the sake of power dissipation(normal operation mode), a gate output switches as rarely as possible, implying highly skewed signal probabilities for 1 or 0. On the other hand, at test mode, signals have probabilities of being 1 or 0 approaching 0.5, so it is possible to exact both stuck-at faults on the wire. Therefore, the goals of synthesis for low power and random pattern testability are achieved. The hardware overhead sof proposed design method are only one primary input for mode selection and AND/OR gate for each redundant connection.

• JSTS:Journal of Semiconductor Technology and Science
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• v.14 no.2
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• pp.184-188
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• 2014

There is a trade-off between read stability and writability under a full-/half-select condition in static random access memory (SRAM). Another trade-off in the minimum operating voltage between the read and write operation also exists. A new peripheral circuit for SRAM arrays, called a variation sensor, is demonstrated here to balance the read/write margins (i.e., to optimize the read/write trade-off) as well as to lower the minimum operation voltage for both read and write operations. A test chip is fabricated using an industrial 45-nm bulk complementary metal oxide semiconductor (CMOS) process to demonstrate the operation of the variation sensor. With the variation sensor, the word-line voltage is optimized to minimize the trade-off between read stability and writability ($V_{WL,OPT}=1.055V$) as well as to lower the minimum operating voltage for the read and write operations simultaneously ($V_{MIN,READ}=0.58V$, $V_{MIN,WRITE}=0.82V$ for supply voltage $(V_{DD})=1.1V$).

• Journal of the Korean Institute of Telematics and Electronics A
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• v.31A no.9
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• pp.156-163
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• 1994

A new circuit simulator for submicron MOS desings was developed by enhancing SPICE3. The minimum conductance stepping, source stepping and pseudo transient methods are applied to improve the convergence. and SECSPICE uses the variation rate of the node volgage in the timestep algorithm. The modified BSIM model was implemented in SECSPICE for submicron MOS designs. And it gives the powerful user environments such as graphic user environments. As the results of test using real measured device data and circuits used in real production desing, we found it gave more accurage results than BSIM and the execution speed was 1.5~2.8 times faster than SPICE3.

• Proceedings of the IEEK Conference
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• 2000.07a
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• pp.343-346
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• 2000

When a feedback bridging fault is activated, oscillation may be generated in output signal lines. If the oscillation is generated, the fault may not be detected by logic testing. Thus, in the past we proposed a current sensor to detect feedback bridging faults by supply current testing. The sensor circuit design requires the maximum frequency of oscillation which is generated when feedback bridging fault is excited as a specification. In this paper, an estimation method of the oscillation frequency is proposed. Also, it is shown by some experiments that the frequency obtained by the method can be used for the sensor design.

• Proceedings of the IEEK Conference
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• 1999.06a
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• pp.397-400
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• 1999

As the result of enhancement of CAD, Design Automation and manufacturing technology, it's on the increasing complexity, integration ratio, data signals, and pin count to IC chips. This brings about difficulties of testing, and incresing test time. Now One of the most cost-consuming procedure as integration ratio increases is the testing step. In this paper, we propose a new method, “Efficient TP(test point) assignment algorithm” using “input grouping”, This is helpful method to reducing test length without losing fault coverage. Experimental results show that proposed method reduces test length remarkably and doesn't miss fault coverage, with low hardware overhead Increasing.

• Progress in Superconductivity and Cryogenics
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• v.2 no.2
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• pp.44-48
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• 2000

The high temperature superconducting bulk can be used as the rotor of an ac motor. This paper presents the fabrication and test results of a ac motor with HTS bulk rotor. The rotor of a conventional squirrel cage induction motor was replaced with cylinder type YBCO bulk. Height and outer diameter of the HTS bulk was 15mm and 46mm, respectively. Eddy current brake using aluminium disk was used to measure the torque of the HTS motor. No load test, locked rotor test and load test were performed to examine the characteristics of the HTS motor. Test results show the motor can rotate at synchronous speed without any special starting circuit. Maximum output power of the constructed HTS motor was 408W.

• Journal of IKEEE
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• v.26 no.4
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• pp.553-559
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• 2022

In this paper, RC snubber circuit design technology for oscillation suppression in half-bridge configuration of cascode gallium nitride (GaN) field effect transistors (FETs) is analyzed. A typical wide band-gap (WBG) device, cascode GaN FET, has excellent high-speed switching characteristics. However, due to such high-speed switching characteristics, a false turn-off problem is caused, and an RC snubber circuit is essential to suppress this. In this paper, the commonly used experimental-based RC snubber design technique and the RC snubber design technique using the root locus method are compared and analyzed. In the general method, continuous circuit changes are required until the oscillation suppression performance requirement is met based on experimental experience . However, in root locus method, the initial value can be set based on the non-oscillation R-C map. To compare the performance of the two aforementioned design methods, a simulation experiment and a switching experiment using an actual double pulse circuit are performed.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.15 no.1
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• pp.299-305
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• 2014

The purpose of this study was to determine the effect of a task-related circuit training in improving the function of lower extremity and quality of life in patient with hemiplegia. A total 25 paients with hemiplegia selected, the volunteers were randomly divided into a task-related circuit training group of 13 people and a treadmill training group of 12 people. The two groups received treadmill training for 30 minutes a day, 5 days a week for 8 weeks. The experimental group was additionally received the task related circuit training for 30 minutes. The assessment comprised of testing the patient's strength, walking, balance ability(strength of knee, balance ability, 10m walking test) and making use of the stroke impact scale. Post treatment, compared to the treadmill training group, task-related circuit training group showed significantly increased strength of knee extensor, flexor and balance ability, stoke impact scale(p<.05). The findings of this study suggest that a task-related circuit training can improve function of lower extremity and quality of life in patient of hemiplegia. Further studies with a greater sample size and a various intervention are needed to generalize the findings of the present study.

• Journal of Advanced Navigation Technology
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• v.21 no.5
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• pp.459-465
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• 2017

In this paper, we introduce the design consideration of the lightning induced transient protection circuit for the indirect lightning strike on the avionics equipment. The lightning induced surge voltage, which is so-called as indirect effects of lightning, may cause a functional failure or physical damage to the electrical and electronic equipment of aircraft. In order to protect the electrical and electronic equipment of aircraft from the indirect effects of lightning, we should analyze the effect of lightning strike on aircraft and consider applying protection design for each avionics device. However, lightning induced transient protection circuits can have unintended consequences because parasitic inductance elements are exist in PCB and TVS diodes. In this paper, we introduce the design method of the protection circuit considering the parasitic inductance of the protection circuit. In addition, we show the result of verification test performed to validate the protection circuits for indirect effects of lightning.