• Proceedings of the KIEE Conference
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• 2007.10a
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• pp.371-372
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• 2007

In this paper we present performance and implementation comparisons of high performance two dimensional forward and inverse Discrete Cosine Transform (2D-DCT/IDCT) algorithm and low power algorithm for $8{\times}8$ 20 DCT and quantization based on partial sum and its corresponding hardware architecture for FPGA in MPEG-4. The architecture used in both low power 20 DCT and 2D IDCT is based on the conventional row-column decomposition method. The use of Fast algorithm and distributed arithmetic(DA) technique to implement the DCT/IDCT reduces the hardware complexity. The design was made using Mentor Graphics Tools for design entry and implementation. Mentor Graphics ModelSim SE6.1f was used for Verilog HDL entry, behavioral Simulation and Synthesis. The 2D DCT/IDCT consumes only 50% of the Operating Power.

• The Transactions of the Korean Institute of Electrical Engineers A
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• v.48 no.3
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• pp.263-269
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• 1999

In this paper, an unifying design algorithm is presented for efficient digital implementation of continuous PID controller using general discrete orthogonal functions. The proposed algorithm is an algebraic method to determine controller parameters, which can unify controller design procedures divided into three ways. A set of linear equations for the controller design are derived from simple algebraic transformation based on general discrete orthogonal functions. By solving these equations, all of the controller parameters can be determined directly and simultaneously, which thus makes the design procedure systematic and straightforward. It does not involve any trial and error procedure, hence the difficulty of conventional approach can be avoided. The simulation results and discussions are given to demonstrate the efficiency of the proposed method.

• Proceedings of the KIEE Conference
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• 1987.07a
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• pp.265-269
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• 1987

In an industrial vision system, a coding technique for binary image is essential to extract useful informations. To reduce the processing time, a hardware implementation of the chain coding algorithm is attemped. For that purpose, the chain coding algorithm is modified so that it is more suitable for a hardware implementation. A hardwired chain coder is also developed and tested with developed vision system. The result shows that the processing time is greatly reduced and that the developed vision system is maybe feasible for real-time applications.

• KSII Transactions on Internet and Information Systems (TIIS)
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• v.12 no.2
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• pp.873-891
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• 2018

This paper suggests an automatic approach to extracting Java method implementation patterns associated with method identifiers using Cascade K-Medoids. Java method implementation patterns indicate recurring implementations for achieving the purpose described in the method identifier with the given parameters and return type. If the implementation is different from the purpose, readers of the code tend to take more time to comprehend the method, which eventually affects to the increment of software maintenance cost. In order to automatically identify implementation patterns and its representative sample code, we first propose three groups of feature vectors for characterizing the Java method signature, method body and their relation. Then, we apply Cascade K-Medoids by enhancing the K-Medoids algorithm with the Calinski and Harrabasez algorithm. As the evaluation of our approach, we identified 16,768 implementation patterns of 7,169 method identifiers from 50 open source projects. The implementation patterns have been validated by the 30 industrial practitioners with from 1 to 6 years industrial experience, resulting in 86% of the precision.

• Journal of Korea Society of Digital Industry and Information Management
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• v.5 no.1
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• pp.51-61
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• 2009

Conventional DES has been not only shown to have a vulnerable drawback to attack method called 'Meet in the Middle', but also to be hard to use that it is because software implementation has a number of problem in real time processing. This paper describes the design and implementation of the expanded DES algorithm using VHDL for resolving the above problems. The main reason for hardware design of an encryption algorithm is to ensure a security against cryptographic attack because there is no physical protection for the algorithm written in software. Total key length of 352 bits is used for the proposed DES. The result of simulation shows that the inputted plaintext in cryptosystem are equal to the outputted that in decryptosystem.

• Journal of the Korean Society for Aeronautical & Space Sciences
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• v.34 no.11
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• pp.35-41
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• 2006

This paper proposes an algorithm for switching LQ(Linear Quadratic) controllers designed at each flight envelope without a bump phenomenon. This algorithm is derived to apply to LQ controller more easily than existing implementation algorithm and is proposed to consider trim points of nonlinear models, which is adequate to real applications. This paper exemplifies the control performance improvement via simulations applied to LQ control of a supersonic test aircraft as a benchmark problem to test the proposed algorithm performance.

• Proceedings of the Korean Institute of Intelligent Systems Conference
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• 2001.12a
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• pp.255-258
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• 2001

This paper is implementation of cellular automata neural network system which is a living creatures' brain using evolving hardware concept. Cellular automata neural network system is based on the development and the evolution, in other words, it is modeled on the ontogeny and phylogeny of natural living things. The proposed system developes each cell's state in neural network by CA. And it regards code of CA rule as individual of genetic algorithm, and evolved by genetic algorithm. In this paper we implement this system using evolving hardware concept Evolving hardware is reconfigurable hardware whose configuration is under the control of an evolutionary algorithm. We design genetic algorithm process for evolutionary algorithm and cells in cellular automata neural network for the construction of reconfigurable system. The effectiveness of the proposed system is verified by applying it to time-series prediction.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.14 no.2
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• pp.141-146
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• 2014

This paper describes the implementation and algorithm of handwritten character recognition using mobile touch screen. The system is consisted of PXA320 processor, capacitive touch panel and QT4 interface. The proposed algorithm extracts pattern characteristics with straight, left circle, right circle on the inputting character. The definition of character is determined by 3-way tree searching method. The performance of proposed algorithm is verified using alphabet character. It is suitable to apply the mobile touch screen because of simple algorithm.

• Journal of the Korean Institute of Telematics and Electronics B
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• v.30B no.11
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• pp.17-26
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• 1993

In this paper, a VlSI architecture for Reed-Solomon (RS) decoder based on the Berlekamp algorithm is proposed. The proposed decoder provided both erasure and error correcting capability. In order to reduc the chip area, we reformulate the Berlekamp algorithm. The proposed algorithm possesses a recursive structure so that the number of cells for computing the errata locator polynomial can be reduced. Moreover, in our approach, only one finite field multiplication per clock cycle is required for implementation, provided an improvement in the decoding speed, and the overall architecture features parallel and pipelined structure, making a real time decoding possible. From the performance evaluation, it is concluded that the proposed VLSI architecture is more efficient in terms of VLSI implementation than the rcursive architecture based on the Euclid algorithm.

• Industrial Engineering and Management Systems
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• v.14 no.4
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• pp.401-412
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• 2015

In this paper, we present a modeling approach to production planning for an actual production line and a heuristic method. We also illustrate the successful implementation of the proposed method on the production line. A heuristic algorithm called the push-back algorithm was designed for a single machine earliness/tardiness production planning with distinct due date. It was developed by combining a minimum slack time rule and shortest processing time rule with a push-back procedure. The results of a numerical experiment on the heuristic's performance are presented in comparison with the results of IBM ILOG CPLEX. The proposed algorithm was applied to an actual case of production planning at Woongjin Chemical, a leading manufacturer of filter products in South Korea. The seven-month execution of our algorithm led to a 24.5% decrease in the company's inventory level, thus demonstrating its practicality and effectiveness.