• Title/Summary/Keyword: impedance network

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Modified Capacitor-Assisted Z-Source Inverter Topology with Enhanced Boost Ability

  • Ho, Anh-Vu;Chun, Tae-Won
    • Journal of Power Electronics
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    • v.17 no.5
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    • pp.1195-1202
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    • 2017
  • This paper presents a novel topology named a modified capacitor-assisted Z-source inverter (MCA-ZSI) based on the traditional ZSI. The impedance network of the proposed MCA-ZSI consists of two symmetrical cells coupled with two capacitors with an X-shape structure, and each cell has two inductors, two capacitors, and one diode. Compared with other topologies based on switched ZSI with the same number of components used at impedance network, the proposed topology provides higher boost ability, lower voltage stress across inverter switching devices, and lower capacitor voltage stress. The improved performances of the proposed topology are demonstrated in the simulation and experimental results.

Estimation Method for Power Distribution Network of Impedance Characteristic on Printed Circuit Board (PCB상의 전력 배분망 설계를 위한 임피던스 계산법)

  • Cho Tae-ho;Park Joong-Ho;Baek Jong-Humn;Kim Seok-Yoon
    • The Transactions of the Korean Institute of Electrical Engineers D
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    • v.52 no.4
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    • pp.246-251
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    • 2003
  • This paper proposes a new methodology for the estimation of impedance characteristics, which is one of the important issue in the power distribution network design of printed circuit boards. The modeling process of the proposed method divides the power distribution network into uniform segment, and each segment is modeled by distributed RLC transmission lines. Then, for the efficient computation of impedance characteristics in frequency domain. the proposed method uses a model-order reduction method.

Method for Designing Parameters of Impedance Network at Quasi Z-Source Inverter (Quasi Z-소스 인버터의 임피던스 네트워크 파라미터 설계방법)

  • Yang, J.H.;Chun, T.W.;Lee, H.H.;Kim, H.G.;Nho, E.C.
    • Proceedings of the KIPE Conference
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    • 2012.07a
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    • pp.203-204
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    • 2012
  • This paper presents the method to design the inductor and capacitor value considering the ripple component that may be generated by three operating states of the Quasi Z-source inverter at the impedance network. Based on the analysis of each operation mode, the equations of the capacitor voltage and inductor current are derived. In order to simplify the design processing, design equations of the impedance network are derived where the capacitor voltage and inductor current are lineared. The validity of the design method is verified with the simulation result using PSIM and experimental result using 32-bit DSP.

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Estimating aquifer location using deep neural network with electrical impedance tomography

  • Sharma, Sunam Kumar;Khambampati, Anil Kumar;Kim, Kyung Youn
    • Journal of IKEEE
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    • v.24 no.4
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    • pp.982-990
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    • 2020
  • Groundwater is essential source of the freshwater. Groundwater is stored in the body of the rocks or sediments, called aquifer. Finding an aquifer is a very important part of the geophysical survey. The best method to find the aquifer is to make a borehole. Single borehole is not a suitable method if the aquifer is not located in the borehole drilled area. To overcome this problem, a cross borehole method is used. Using a cross borehole method, we can estimate aquifer location more precisely. Electrical impedance tomography is use to estimate the aquifer location inside the subsurface using the cross borehole method. Electrodes are placed inside each boreholes and area between these boreholes are analysed. An aquifer is a non-uniform structure with complex shape which can represented by the truncated Fourier series. Deep neural network is evaluated as an inverse problem solver for estimating the aquifer boundary coefficients.

An equivalent Circuit Model of Transformer Coupled Plasma Source (축전 용량이 고려된 평판형 유도 결합 플라즈마 원의 등가회로 모델)

  • Kim, Jeong-Mi;Kwon, D.C.;Yoon, N.S.
    • Proceedings of the KIEE Conference
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    • 2002.07c
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    • pp.1760-1762
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    • 2002
  • In this work we develop an equivalent circuit model of TCP(transformer coupled plasma) source and investigate matching characteristic. The developed circuit model includes transmission line, standard-type impedance matching network and displacement current in the plasma source. The impedance of TCP is calculated by previously developed program for various source parameters and dependance of components of matching impedance on the value of source impedance is investigated.

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DRAM Package Substrate Using Via Cutting Structure (비아 절단 구조를 사용한 DRAM 패키지 기판)

  • Kim, Moon-Jung
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.48 no.7
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    • pp.76-81
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    • 2011
  • A new via cutting structure in 2-layer DRAM package substrate has been fabricated to lower its power distribution network(PDN) impedance. In new structure, part of the via is cut off vertically and its remaining part is designed to connect directly with the bonding pad on the package substrate. These via structure and substrate design not only provide high routing density but also improve the PDN impedance by shortening effectively the path from bonding pad to VSSQ plane. An additional process is not necessary to fabricate the via cutting structure because its structure is completed at the same time during a process of window area formation. Also, burr occurrence is minimized by filling the via-hole inside with a solder resist. 3-dimensional electromagnetic field simulation and S-parameter measurement are carried out in order to validate the effects of via cutting structure and VDDQ/VSSQ placement on the PDN impedance. New DRAM package substrate has a superior PDN impedance with a wide frequency range. This result shows that via cutting structure and power/ground placement are effective in reducing the PDN impedance.

Experimental Studies on Neural Network Force Tracking Control Technique for Robot under Unknown Environment (미정보 환경 하에서 신경회로망 힘추종 로봇 제어 기술의 실험적 연구)

  • Jeong, Seul;Yim, Sun-Bin
    • Journal of Institute of Control, Robotics and Systems
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    • v.8 no.4
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    • pp.338-344
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    • 2002
  • In this paper, neural network force tracking control is proposed. The conventional impedance function is reformulated to have direct farce tracking capability. Neural network is used to compensate for all the uncertainties such as unknown robot dynamics, unknown environment stiffness, and unknown environment position. On line training signal of farce error for neural network is formulated. A large x-y table is built as a test-bed and neural network loaming algorithm is implemented on a DSP board mounted in a PC. Experimental studies of farce tracking on unknown environment for x-y table robot are presented to confirm the performance of the proposed technique.

RF Impedance Matching Algorithm Using Phase Detector (임피던스 정합장치 내 위상센서를 이용한 RF정합 알고리즘 연구)

  • Kim, Hwanggyu;Yang, Jinwoo;Kang, Sukho;Choi, Daeho;Hong, Sang Jeen
    • Journal of the Semiconductor & Display Technology
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    • v.21 no.2
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    • pp.32-37
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    • 2022
  • As semiconductors become finer, equipment must perform precise and accurate processes to achieve the desired wafer fabrication requirement. Radio frequency power delivery system in plasma system plays a critical role to generate the plasma, and the role of impedance matching unit is critical to terminate the reflected radio frequency power by modifying the impedance of the matching network in the plasma equipment. Impedance matching unit contains one fixed inductor and two variable vacuum capacitors whose positions are controlled two step motors. Controlling the amount of vacuum variable capacitor should be made as soon as possible when the mismatched impedance is detected. In this paper, we present the impedance matching algorithm using the phase sensor.

The Estimation of the Target Position and Size Using Multi-layer Neural Network in Electrical Impedance Tomography (전기 임피던스 단층촬영법에서 다층 신경회로망을 이용한 표적의 위치와 크기 추정)

  • Kim, Ji-Hoon;Kim, Chan-Yong;Cho, Tae-Hyun;Lee, In-Soo
    • The Journal of Korean Institute of Information Technology
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    • v.16 no.11
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    • pp.35-41
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    • 2018
  • Electrical impedance tomography (EIT) is a kind of nondestructive testing technique that obtains the internal resistivity distribution from the voltages measured at the electrodes located outside the area of interest. However, an image reconstruction problem in EIT has innate non-linearity and ill-posedness, so that it is difficult to obtain satisfactory reconstructed results. In general, a neural network can efficiently model the input and output relationships of a non-linear system. This paper proposes a method for estimating the position and size of a circular target using a multi-layer neural network. To verify the performance of the proposed method, neural network was trained and various computer simulations were performed and satisfactory performance was verified.

Classification of High Impedance Fault Patterns by Recognition of Linear Prediction coefficients (선형 예측 계수의 인식에 의한 고저항 지락사고 유형의 분류)

  • Lee, Ho-Seob;Kong, Seong-Gon
    • Proceedings of the KIEE Conference
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    • 1996.07b
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    • pp.1353-1355
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    • 1996
  • This paper presents classification of high impedance fault pattern using linear prediction coefficients. A feature of neutral phase current is extracted by the linear predictive coding. This feature is classified into faults by a multilayer perceptron neural network. Neural network successfully classifies test data into three faults and one normal state.

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