• Current Photovoltaic Research
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• 제2권2호
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• pp.41-47
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• 2014

Extensive investigation on silicon based thin film reveals a wide range of film characteristics, from low optical gap to high optical gap, from amorphous to micro-crystalline silicon etc. Fabrication of single junction, tandem and triple junction solar cell with suitable materials, indicate that fabrication of solar cell of a relatively moderate efficiency is possible with a better light induced stability. Due to these investigations, various competing materials like wide band gap silicon carbide and silicon oxide, low band gap micro-crystalline silicon and silicon germanium etc were also prepared and applied to the solar cells. Such a multi-junction solar cell can be a technologically promising photo-voltaic device, as the external quantum efficiency of such a cell covers a wider spectral range.

• 한국전기전자재료학회논문지
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• 제29권12호
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• pp.750-758
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• 2016

For the channel doping of shallow junction and retrograde well formation in CMOS, indium can be implanted in silicon. The retrograde doping profiles can serve the needs of channel engineering in deep MOS devices for punch-through suppression and threshold voltage control. Indium is heavier element than B, $BF_2$ and Ga ions. It also has low coefficient of diffusion at high temperatures. Indium ions can be cause the erode of wafer surface during the implantation process due to sputtering. For the ultra shallow junction, indium ions can be implanted for p-doping in silicon. UT-MARLOWE and SRIM as Monte carlo ion-implant models have been developed for indium implantation into single crystal and amorphous silicon, respectively. An analytical tool was used to carry out for the annealing process from the extracted simulation data. For the 1D (one-dimensional) and 2D (two-dimensional) diffused profiles, the analytical model is also developed a simulation program with $C^{{+}{+}}$ code. It is very useful to simulate the indium profiles in implanted and annealed silicon autonomously. The fundamental ion-solid interactions and sputtering effects of ion implantation are discussed and explained using SRIM and T-dyn programs. The exact control of indium doping profiles can be suggested as a future technology for the extreme shallow junction in the fabrication process of integrated circuits.

• 전자공학회논문지
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• 제50권1호
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• pp.239-245
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• 2013

발전소 내 고압 단자대 및 전력구 케이블 인입부에서 주변 전력기기들의 지속적인 진동 및 순간적인 충격의 발생으로 케이블 단자 또는 접속부 접촉점에 열화가 발생하는 사고가 일어난다. 접촉점에서의 열화 발생은 큰 사고로 이어질 수 있으며 안정적으로 전력을 공급해야 하는 발전소에서는 열화 발생을 예측하기 위한 다양한 연구가 시도되고 있다. 이에 비접촉식 적외선 센서를 이용하여 온도를 측정하는 방식이 있으며 이러한 방식의 궁극적인 목적은 측정하고자 하는 대상체를 최적의 거리에서 감시함으로 접촉점의 열화 발생뿐 아니라 센서 측정범위 내의 열화의 상태도 감시하는 데 있다. 연결부 온도를 측정하고 열화 상태를 실시간 감시하여 사용자에게 가시, 가청 알람을 주어 사용자가 열화사고를 인지하여 미연에 방지할 수 있게 한다. 그러나 이러한 시스템을 구축하기 위해서는 감시 장치를 설치, 운영해야 하는 어려움이 있다. 본 연구에서는 설치 용이성을 고려하여 소출력 배터리 동작모듈로 접속부의 온도를 측정하고 이를 감시할 수 있는 적외선센서를 이용한 무선감시시스템을 개발하였다.

• 한국진공학회:학술대회논문집
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• 한국진공학회 2014년도 제46회 동계 정기학술대회 초록집
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• pp.320-320
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• 2014

Amorphous silicon alloy (a-Si) solar cells and modules have been receiving a great deal of attention as a low-cost alternate energy source for large-scale terrestrial applications. Key to the achievement of high-efficiency solar cells using the multi-junction approach is the development of high quality, low band-gap materials which can capture the low-energy photons of the solar spectrum. Several cell designs have been reported in the past where grading or buffer layers have been incorporated at the junction interface to reduce carrier recombination near the junction. We have investigated profiling the composition of the a-SiGe alloy throughout the bulk of the intrinsic material so as to have a built-in electrical field in a substantial portion of the intrinsic material. As a result, the band gap mismatch between a-Si:H and $a-Si_{1-x}Ge_x:H$ creates a barrier for carrier transport. Previous reports have proposed a graded band gap structure in the absorber layer not only effectively increases the short wavelength absorption near the p/i interface, but also enhances the hole transport near the i-n interface. Here, we modulated the GeH4 flow rate to control the band gap to be graded from 1.75 eV (a-Si:H) to 1.55 eV ($a-Si_{1-x}Ge_x:H$). The band structure in the absorber layer thus became like a U-shape in which the lowest band gap was located in the middle of the i-layer. Incorporation of this structure in the middle and top cell of the triple-cell configuration is expected to increase the conversion efficiency further.

• 전자공학회논문지A
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• 제31A권12호
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• pp.80-90
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• 1994

To develop VLSI of higher packing density with 0.5.mu.m gate length of less, semiconductor devices require shallow junction with higher doping concentration. the most common method to form the shallow junction is ion implantation, but in order to remove the implantation induced defect and activate the implanted impurities electrically, ion-implanted Si should be annealed at high temperature. In this annealing, impurities are diffused out and redistributed, creating deep PN junction. These make it more difficult to form the shallow junction. Accordingly, to miimize impurity redistribution, the thermal-budget should be kept minimum, that is. RTA needs to be used. This paper reports results of the diffusion characteristics of PSG film by varying Phosphorus weitht %/ Times and temperatures of RTA. From the SIMS.ASR.4-point probe analysis, it was found that low sheet resistance below 100 .OMEGA./ㅁand shallow junction depths below 0.2.mu.m can be obtained and the surface concentrations are measured by SIMS analysis was shown to range from 2.5*10$^{17}$ aroms/cm$^{3}$~3*10$^{20}$ aroms/cm$^{3}$. By depending on the RTA process of PSG film on Si, LDD-structured nMOSFET was fabricated. The junction depths andthe concentration of n-region were about 0.06.mu.m. 2.5*10$^{17}$ atom/cm$^{-3}$ , 4*10$^{17}$ atoms/cm$^{-3}$ and 8*10$^{17}$ atoms/cm$^{3}$, respectively. As for the electrical characteristics of nMOS with phosphorus junction for n- region formed by RTA, it was found that the characteristics of device were improved. It was shown that the results were mainly due to the reduction of electric field which decreases hot carriers.

• Journal of information and communication convergence engineering
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• 제8권6호
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• pp.623-629
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• 2010

A geographical routing protocol is typically utilized for a route selection of VANET. Even if it is conceptually well adapted into VANET, message delivery tends to be unreliable with frequent network partitions, which mainly come from the inherent characteristics such as high mobility and irregular traffic density. In this paper, we deal with a method to enable reliable message delivery with reflecting the traffic density on routing decision. By concatenating the message delivery cost of each of inbetween junction section, $1^{st}$ and $2^{nd}$ shortest paths are initially determined. When it is not possible to deliver the message on a junction on the 1st path, we utilize two novel ideas, that is, letting the message stay on the junction to find out a new relay node, and putting a replicated copy to reach via a detour path. By using the NS-2 network simulator, our method has been examined in terms of message delivery rate and delay. It shows that our method is much efficient than the other method in the low density environment, while it brings similar results in the high density environment.

• 한국표면공학회지
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• 제54권5호
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• pp.207-212
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• 2021

The mechanical and electrical characteristics can be improved in 3D stacked IC technology which can accomplish the ultra-high integration by stacking more semiconductor chips within the limited package area through the Cu direct bonding method minimizing the performance degradation to the bonding surface to the inorganic compound or the oxide film etc. The surface was treated in a ultrasonic washer using a diamond abrasive to remove other component substances from the prepared cast plate substrate surface. FE-SEM was used to analyze the bonding characteristics of the bonded copper substrates, and the cross section of the bonded Cu conjugates at the sintering junction temperature of 100 ℃, 150 ℃, 200 ℃, 350 ℃ and the pressure of 2303 N/cm² and 3087 N/cm². At 2303 N/cm², the good bonding of copper substrate was confirmed at 350 ℃, and at the increased pressure of 3087 N/cm², the bonding condition of Cu was confirmed at low temperature junction temperature of 200 ℃. However, the recrystallization of Cu particles was observed due to increased pressure of 3087 N/cm² and diffusion of Cu atoms at high temperature of 350 ℃, which can lead to degradation in semiconductor manufacturing.

• Current Photovoltaic Research
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• 제3권2호
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• pp.45-49
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• 2015

In the past few decade's researchers, scientists, engineers of photovoltaic (PV) industry are working towards low cost high efficiency Si solar cells. Over the last decade the interest in back contact solar cell has been acquiring as well as a gradual introduction to industrial applications is increasing. As an alternative to conventional solar cells with a front and rear contact, the back-contact cells has remained a research topic. The aim of this work is to present a comprehensive summary of results incurred in the back contact back junction solar cells such as interdigitated back-contact (IBC), emitter wrap-through (EWT) and metallization wrap-through (MWT) over the years.

• 한국초전도학회:학술대회논문집
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• 한국초전도학회 1999년도 High Temperature Superconductivity Vol.IX
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• pp.238-241
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• 1999

Analog-to-digital converter has attracted a lot of interests as one of the most prospective area of an application of Josephson Junction technology. Recently, the development of a digital-to-analog converter has been pursued to achieved the high performance. One of the main advantage in using single flux quantum logic in a digital-to-analog converter is the low voltage drop in a single Josephson Junction and hence the resolution of the output voltage of this digital-to-analog converter can be very high. In this work, we have used a software, called WRspice, to study a voltage multiplier circuit which is the basic block in building a digital-to-analog circuit. In simulation, we operated a voltage multiplier with .4 Josephson Junctions per stage and studied the dependence on the circuit bias currents and the circuit inductors of the voltage multiplier. Our simulation results showed a fast operation and reasonable circuit margins.

• JSTS:Journal of Semiconductor Technology and Science
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• 제13권6호
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• pp.546-550
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• 2013

We propose a novel negative differential resistance (NDR) device with ultra-high peak-to-valley current ratio (PVCR) by combining pn junction diode with depletion mode nanowire (NW) transistor, which suppress the valley current with transistor off-leakage level. Band-to-band tunneling (BTBT) Esaki diode with degenerately doped pn junction can provide multiple switching behavior having multi-peak and valley currents. These multiple NDR characteristics can be controlled by doping concentration of tunnel diode and threshold voltage of NW transistor. By designing our NDR device, PVCR can be over $10^4$ at low operation voltage of 0.5 V in a single peak and valley current.