• Journal of KIISE:Computing Practices and Letters
• /
• v.13 no.4
• /
• pp.213-225
• /
• 2007

Flash memory is widely used as a storage device for potable equipments such as digital cameras, MP3 players and cellular phones because of its characteristics such as its large volume and nonvolatile feature, low power consumption, and good performance. However, a block in flash memories should be erased to write because of its hardware characteristic which is called as erase-before-write architecture. The erase operation is much slower than read or write operations. FTL is used to overcome this problem. We compared the performance of the existing FTL algorithms on Windows-based OS. We have developed a tool called FTL APAT in order to gather I/O patterns of the disk and analyze the performance of the FTL algorithms. It is the log buffer scheme with full associative sector translation(FAST) that the performance is best.

• Journal of KIISE:Computing Practices and Letters
• /
• v.16 no.11
• /
• pp.1126-1130
• /
• 2010

Research on intelligent robot is in active progress as the next generation IT education area. Since intelligent robots are closely related to the real human world, they should provide human behaviors or judging ability as their functions. For this reason, research is recently done not only on diverse hardware of robot education but also on service component architecture which includes various functions. In this paper we propose a study on learning to creative solve problems using RDS(Robotics Developer Studio). RDS is a software tool to control or program intelligence robot as a software module. Using service component framework which considers standardization of the integrated development of intelligent robot, we expect to provide 3-dimensional visual simulation environment, and save time and costs in education the environment for the intelligence robot experiment.

• Journal of Information Processing Systems
• /
• v.14 no.3
• /
• pp.569-589
• /
• 2018

Cloud computing, also known as "country as you go", is used to turn any computer into a dematerialized architecture in which users can access different services. In addition to the daily evolution of stakeholders' number and beneficiaries, the imbalance between the virtual machines of data centers in a cloud environment impacts the performance as it decreases the hardware resources and the software's profitability. Our axis of research is the load balancing between a data center's virtual machines. It is used for reducing the degree of load imbalance between those machines in order to solve the problems caused by this technological evolution and ensure a greater quality of service. Our article focuses on two main phases: the pre-classification of tasks, according to the requested resources; and the classification of tasks into levels ('odd levels' or 'even levels') in ascending order based on the meta-heuristic "Bat-algorithm". The task allocation is based on levels provided by the bat-algorithm and through our mathematical functions, and we will divide our system into a number of virtual machines with nearly equal performance. Otherwise, we suggest different classes of virtual machines, but the condition is that each class should contain machines with similar characteristics compared to the existing binary search scheme.

• The KIPS Transactions:PartC
• /
• v.9C no.2
• /
• pp.213-220
• /
• 2002

Distributed competing system gives a new system architecture to be taken into consideration for solving the problems of interoperability of heterogeneous systems. In the present paper, CORBA based on multi-threaded interoperates with software blocks at physically isolated hardware. We show how archives optimal CORBA system from analysis of required functions, implementations of protocols and benchmarking of system performance in the Open Multi-service Network System Environment. The core features of our CORBA system are restricted Quality of Service based on priority, timeout service and exception status information notify to the related software blocks. And the objectives are design and implementation of high performance multi-threaded middleware and satisfied with extendibility, flexibility and stability of CORBA platform.

• The KIPS Transactions:PartA
• /
• v.9A no.4
• /
• pp.459-466
• /
• 2002

Modern embedded system employs a hybrid architecture which contains a general micro processor and reconfigurable devices such as FPGAS to retain flexibility and to meet timing constraints. It is a hard and important problem for embedded system designers to explore and find a right system configuration, which is known as design space exploration (DSE). With DES, it is possible to predict a final system configuration during the design phase before physical implementation. In this paper, we implement a timing analysis simulator for a DSE on a hybrid embedded system. The simulator, integrating exiting timing analysis tools for hardware and software, is designed by extending Y-chart approach, which allows quantitative performance analysis by varying design parameters. This timing analysis simulator is expected to reduce design time and costs and be used as a core module of a DSE for a hybrid embedded system.

• The KIPS Transactions:PartC
• /
• v.10C no.4
• /
• pp.463-470
• /
• 2003

Many types of switching fabrics have been proposed for use in ATM networks. Multistage Interconnection Networks (MINs) constitute a large class of ATM switching systems that are widely used in today´s internetworking. One of the most veil-known types of multistage networks is the banyan network. The banyan network is attractive for its simple routing scheme and low hardware complexity, but its throughput is very limited due to internal blocking and output contention. In this paper, we propose an input-buffered dual-banyan switch model with multiple switching fabric between switch input and output to avoid internal and Head-of Line blocking. By performance analysis and simulation, we show that our model has a lower ceil delay and 96% throughput which is much better than other banyan-type switch architecture.

• Journal of Advanced Navigation Technology
• /
• v.17 no.6
• /
• pp.705-711
• /
• 2013

In this paper, we present a low-complexity non-coherent demodulation algorithm and hardware architecture for LR-WPAN systems which can support the variable data rate for various applications. The need for LR-WPAN systems that can support the variable data rate is increasing due to the emergence of various sensor applications. Since the existing symbol based double correlation (SBDC) algorithm requires the increase of complexity to support the variable data rate, we propose the sample based double correlation (SPDC) algorithm which can be implemented without the increase of complexity. The proposed non-coherent demodulator was designed by verilog HDL and implemented with FPGA prototype board.

• Journal of the Korea Computer Industry Society
• /
• v.6 no.3
• /
• pp.465-476
• /
• 2005

The wireless sensor network consists of a number of sensor nodes which have physical constraints. Each sensor node senses surrounding environments and sends the sensed information to Sink. In order to alleviate the inherent vulnerability in security of the wireless sensor nodes with the hardware constraints, the lightweight security protocol is needed and a variety of research is ongoing. In this paper, we propose a non-hierarchical sensor network and a security protocol that is suitable for monitoring man-made objects such as bridges. This paper, furthermore, explores a two-layer authentication, key distribution scheme which distributes the key and location of a sensor node in advance, and an effective security routing protocol which can take advantage of the Sleep and Awake state. This also results in the increased data transfer rate by increasing the number of alternative routing paths and the reduced energy consumption rate.

• Korean Journal of Remote Sensing
• /
• v.25 no.6
• /
• pp.547-557
• /
• 2009

LIDAR (LIght Detection And Ranging) is an active remote sensing technology which provides 3D coordinates of the Earth's surface by performing range measurements from the sensor. Early small footprint LIDAR systems recorded multiple discrete returns from the back-scattered energy. Recent advances in LIDAR hardware now make it possible to record full digital waveforms of the returned energy. LIDAR waveform decomposition involves separating the return waveform into a mixture of components which are then used to characterize the original data. The most common statistical mixture model used for this process is the Gaussian mixture. Waveform decomposition plays an important role in LIDAR waveform processing, since the resulting components are expected to represent reflection surfaces within waveform footprints. Hence the decomposition results ultimately affect the interpretation of LIDAR waveform data. Computational requirements in the waveform decomposition process result from two factors; (1) estimation of the number of components in a mixture and the resulting parameter estimates, which are inter-related and cannot be solved separately, and (2) parameter optimization does not have a closed form solution, and thus needs to be solved iteratively. The current state-of-the-art airborne LIDAR system acquires more than 50,000 waveforms per second, so decomposing the enormous number of waveforms is challenging using traditional single processor architecture. To tackle this issue, four parallel LIDAR waveform decomposition algorithms with different work load balancing schemes - (1) no weighting, (2) a decomposition results-based linear weighting, (3) a decomposition results-based squared weighting, and (4) a decomposition time-based linear weighting - were developed and tested with varying number of processors (8-256). The results were compared in terms of efficiency. Overall, the decomposition time-based linear weighting work load balancing approach yielded the best performance among four approaches.

• Journal of Broadcast Engineering
• /
• v.26 no.2
• /
• pp.167-174
• /
• 2021

Recently, deep learning technology is widely used in various computer vision applications, such as object recognition, classification, and image generation. In particular, the deep learning-based super-resolution has been gaining significant performance improvement. Fast super-resolution convolutional neural network (FSRCNN) is a well-known model as a deep learning-based super-resolution algorithm that output image is generated by a deconvolutional layer. In this paper, we propose an FPGA-based convolutional neural networks accelerator that considers parallel computing efficiency. In addition, the proposed method proposes Optimal-FSRCNN, which is modified the structure of FSRCNN. The number of multipliers is compressed by 3.47 times compared to FSRCNN. Moreover, PSNR has similar performance to FSRCNN. We developed a real-time image processing technology that implements on FPGA.