• 한국정밀공학회지
• /
• 제21권7호
• /
• pp.22-29
• /
• 2004

As a result of high integration of semiconductor device, the global planarization of multi-layer structures is necessary. So the chemical mechanical polishing(CMP) is widely applied to manufacturing the dielectric layer and metal line in the semiconductor device. CMP process is under influence of polisher, pad, slurry, and process itself, etc. In comparison with the general CMP which uses the slurry including abrasives, fixed abrasive pad takes advantage of planarity, resulting from decreasing pattern selectivity and defects such as dishing & erosion due to the reduction of abrasive concentration especially. This paper introduces the manufacturing technique of fixed abrasive pad using hydrophilic polymers with swelling characteristic in water and explains the self-conditioning phenomenon. And the tungsten CMP using fixed abrasive pad achieved the good conclusion in terms of the removal rate, non-uniformity, surface roughness, material selectivity, micro-scratch free contemporary with the pad life-time.

• 한국전기전자재료학회:학술대회논문집
• /
• 한국전기전자재료학회 2003년도 제5회 학술대회 논문집 일렉트렛트 및 응용기술연구회
• /
• pp.109-112
• /
• 2003

Recently, CMP (Chemical mechanical polishing) technology has been widely used for global planarization of multi-level interconnection for ULSI applications. However, COO (cost of ownership) and COC (cost of consumables) were relatively increased because of expensive slurry. In this paper, we have studied the possibility of recycle of reused silica slurry in order to reduce the costs of CMP slurry. Also, we have collected the silica abrasive powders by filtering after subsequent CMP process for the purpose of abrasive particle recycling. And then, we annealed the collected abrasive powders to promote the mechanical strength of reduced abrasion force. Finally, we compared the CMP characteristics between self-developed KOH-based silica abrasive slurry and original slurry. As our experimental results, we obtained the comparable removal rate and good planarity with commercial products. Consequently, we can expect the saving of high cost slurry.

• 한국전기전자재료학회논문지
• /
• 제14권1호
• /
• pp.1-5
• /
• 2001

STI(shallow trench isolation)-CMP(chemical mechanical polishing) process have been substituted for LOCOS(local oxidation of silicon) process to obtain global planarization in the below sub-0.5㎛ technology. However TI-CMP process, especially TI-CMP with RIE(reactive ion etching) etch back process, has some kinds of defect like nitride residue, torn oxide defect, etc. In this paper, we studied how to reduced torn oxide defects after STI-CMP with RIE etch back processed. Although torn oxide defects which can occur on trench area is not deep and not severe, torn oxide defects on moat area is not deep and not severe, torn oxide defects on moat area is sometimes very deep and makes the yield loss. Thus, we did test on pattern wafers which go through trench process, APECVD process, and RIE etch back process by using an IPEC 472 polisher, IC1000/SUVA4 PAD and KOH base slurry to reduce the number of torn defects and to study what is the origin of torn oxide defects.

• 한국전기전자재료학회논문지
• /
• 제18권9호
• /
• pp.787-792
• /
• 2005

Chemical mechanical polishing(CMP) has become the process of choice for modem semiconductor devices to achieve both local and global planarization. CMP is a complex process which depends on numerous variables such as macro, micro and nano-geometry of pad, relative velocity between pad and wafer stiffness and dampening characteristics of pad, slurry, pH, chemical components of slurry, abrasive concentration, abrasive size, abrasive shape, etc. Especially, an oxidizer of chemical components is very important remove a target material in metal CMP process. This paper introduces the effect of oxidizer such as $H_2O_2,\;Fe(NO_3)_3\;and\;KIO_3$ in slurry for tungsten which is used in via or/and plug. Finally the duplex reacting mechanism of $oxidizer(H_2O_2)$ through adding the $catalyst(Fe(NO_3)_3)$ could acquire the sufficient removal rate in tungsten CMP.

• 대한전기학회논문지:전기물성ㆍ응용부문C
• /
• 제53권3호
• /
• pp.128-132
• /
• 2004

The perovskite ferroelectric materials of the PZT, SBT and BST series will attract much attention for application to ULSI devices. Among these materials, the BST ($Ba_0.6$$Sr_0.4$/$TiO_3$) is widely considered the most promising for use as an insulator in the capacitors of DRAMS beyond 1 Gbit and high density FRAMS. Especially, BST thin films have a good thermal-chemical stability, insulating effect and variety of Phases. However, BST thin films have problems of the aging effect and mismatch between the BST thin film and electrode. Also, due to the high defect density and surface roughness at grain boundarys and in the grains, which degrades the device performances. In order to overcome these weakness, we first applied the chemical mechanical polishing (CMP) process to the polishing of ferroelectric film in order to obtain a good planarity of electrode/ferroelectric film interface. BST ferroelectric film was fabricated by the sol-gel method. And then, we compared the surface characteristics before and after CMP process of BST films. We expect that our results will be useful promise of global planarization for FRAM application in the near future.

• 한국전기전자재료학회:학술대회논문집
• /
• 한국전기전자재료학회 2001년도 춘계학술대회 논문집 반도체재료
• /
• pp.30-33
• /
• 2001

Chemical mechanical polishing(CMP) process has been widely used to planarize dielectrics, which can apply to employed in integrated circuits for sub-micron technology. Despite the increased use of CMP process, it is difficult to accomplish the global planarization of free-defects in inter-level dielectrics (ILD). Especially, defects like micro-scratch lead to severe circuit failure, and affects yield. CMP slurries can contain particles exceeding $1{\mu}m$ size, which could cause micro-scratch on the wafer surface. The large particles in these slurries may be caused by particle agglomeration in slurry supply line. To reduce these defects, slurry filtration method has been recommended in oxide CMP. In this work, we have studied the effects of filtration and the defect trend as a function of polished wafer count using various filters in inter-metal dielectric(IMD)-CMP. The filter installation in CMP polisher could reduce defect after IMD-CMP. As a result of micro-scratches formation, it shows that slurry filter plays an important role in determining consumable pad lifetime.

• 한국전기전자재료학회:학술대회논문집
• /
• 한국전기전자재료학회 2001년도 춘계학술대회 논문집 반도체재료
• /
• pp.34-37
• /
• 2001

As the integrated circuit device shrinks to smaller dimensions, chemical mechanical polishing (CMP) process was required for the global planarization of inter-metal dielectric (IMD) layer with free-defect. However, as the inter-metal dielectrics (IMD) layer gets thinner, micro-scratches are becoming as major defects. Micro-scratches are generated by agglomerated slurry, solidified and attached slurry in pipe line of slurry supply system. To prevent agglomerated slurry particle from inflow, we installed 0.5${\mu}m$ POU (point of use) filter, which is depth-type filter and has 80% filtering efficiency for the $1.0{\mu}m$ size particle. In this paper, we studied the relationship between defect generation and pad count to understand the exact efficiency of the slurry filtration, and to find out the appropriate pad usage. Our preliminary results showed that it is impossible to prevent defect-causing particles perfectly through the depth-type filter. Thus, we suggest that it is necessary to optimize the flow rate of slurry to overcome depth type filters weak-point, and to install the high spray of de-ionized Water (DIW) with high pressure.

• 한국전기전자재료학회:학술대회논문집
• /
• 한국전기전자재료학회 2006년도 추계학술대회 논문집 Vol.19
• /
• pp.380-381
• /
• 2006

Chemical mechanical polishing (CMP) technology has been widely used for global planarization of multi-level interconnection for ULSI applications. However, the cost of ownership and cost of consumables are relatively high because of expensive slurry. In this paper, we studied the mixed abrasive slurry (MAS). In order to save the costs of slurry, the original silica slurry was diluted by de-ionized water (DIW). And then, $ZrO_2$, $CeO_2$, and $MnO_2$ abrasives were added in the diluted slurry in order to promote the mechanical force of diluted slurry. We have also investigate the possibility of mixed abrasive slurry for the oxide CMP application.

• 한국전기전자재료학회:학술대회논문집
• /
• 한국전기전자재료학회 2004년도 추계학술대회 논문집 Vol.17
• /
• pp.707-710
• /
• 2004

Chemical mechanical polishing (CMP) process has been widely used to planarize dielectric layers, which can be applied to the integrated circuits for sub-micron technology. Despite the increased use of CMP process, it is difficult to accomplish the global planarization of in the defect-free inter-level dielectrics (ILD). In this paper, we have investigated slurry properties and CMP performance of silicon dioxide (oxide) as a function of different temperature of slurry. Thermal effects on the silica slurry properties such as pH, particle size, conductivity and zeta potential were studied. Moreover, the relationship between the removal rate (RR) with WIWNU and slurry properties caused by changes of temperature were investigated. Therefore, the understanding of these temperature effects provides a foundation to optimize an oxide CMP Process for ULSI multi-level interconnection technology.

• 한국전기전자재료학회:학술대회논문집
• /
• 한국전기전자재료학회 2004년도 추계학술대회 논문집 Vol.17
• /
• pp.731-734
• /
• 2004

As the integrated circuit device shrinks to the smaller dimension, the chemical mechanical polishing (CMP) process was required for the global planarization of inter-metal dielectric(IMD) layer with free-defect. Polishing pads play a key role in CMP, which has been recognized as a critical step to improve the topography of wafers for semiconductor fabrication. It is investigated the performance of $SiO_2-CMP$ process using commercial silica slurry as a pad conditioning temperature increased after CMP process. This study also showed the change of SEM images in the pore geometry on the CMP pad surface after use with a different pad conditioning temperature.