• Proceedings of the IEEK Conference
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• 2001.06b
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• pp.29-32
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• 2001

In this paper, the thermal oxidation behaviors and the electrical characteristics of the thermal oxide grown on SiC are discussed. For these studies the oxide layers with various thickness were on SiC in wet $O_2$ or dry $O_2$ at l15$0^{\circ}C$ and the MOS capacitors using the 350$\AA$ gate oxide grown in wet $O_2$ were fabricated and electrically characterized. It was found from the experimental results that the oxidation rate of SiC with the Si-face and with the carbon-face were about 10% and 50% of oxidation rate of Si. The C-V measurement results of the SiC oxide showed abnormal hysterisis properties which had ever been not observed for the Si oxide. And the hysterisis behavior was seen more significant when initial bias voltage was more negative or more positive. The hysterisis property of the SiC oxide was believed to be due the substantial amount of the deep level traps to exist at the interface between the oxide and the SiC substrate. The leakage of the SiC oxide was found to be one order larger than the Si oxide, but the breakdown strength was almost equal to that of the Si oxide.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.21 no.8
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• pp.1465-1470
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• 2017

In conventional MOSFETs, the silicon thickness is always larger than inversion layer, so that the drain induced barrier lowering (DIBL) is expressed as a function of oxide thickness and channel length regardless of silicon thickness. However, since the silicon thickness is fully depleted in the sub-10 nm low doped double gate (DG) MOSFET, the conventional SPICE model for DIBL is no longer available. Therefore, we propose a novel DIBL SPICE model for DGMOSFETs. In order to analyze this, a thermionic emission and the tunneling current was obtained by the potential and WKB approximation. As a result, it was found that the DIBL was proportional to the sum of the top and bottom oxide thicknesses and the square of the silicon thickness, and inversely proportional to the third power of the channel length. Particularly, static feedback coefficient of SPICE parameter can be used between 1 and 2 as a reasonable parameter.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2009.06a
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• pp.3-4
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• 2009

As device process technology advances, effective channel length, the thickness of gate oxide, and supply voltage decreases. This paper describes a novel electrostatic discharge (ESD) protection device which has current feedback for high ESD immunity. A conventional Gate-Grounded NMOS (GGNMOS) transistor has only one ESD current path, which makes, the core circuit be in the safe region, so an GGNMOS transistor has low current immunity compared with our device which has current feedback path. To simulate our device, we use conventional $0.18\;{\mu}m$ technology parameters with a gate oxide thickness of $43\;{\AA}$ and power supply voltage of 1.8 V. Our simulation results indicate that the area of our ESD protection, device can be smaller than a GGNMOS transistor, and ESD immunity is better than a GGNMOS transistor.

• Journal of information and communication convergence engineering
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• v.5 no.1
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• pp.45-49
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• 2007

The analytical transport model in subthreshold regime for double gate MOSFET has been presented to analyze the short channel effects such as subthreshold swing, threshold voltage roll-off and drain induced barrier lowering. The present approach includes the quantum tunneling of carriers through the source-drain barrier. Poisson equation is used for modeling thermionic emission current, and Wentzel-Kramers-Brillouin approximations are applied for modeling quantum tunneling current. This model has been used to investigate the subthreshold operations of double gate MOSFET having the gate length of the nanometer range with ultra thin gate oxide and channel thickness under sub-20nm. Compared with results of two dimensional numerical simulations, the results in this study show good agreements with those for subthreshold swing and threshold voltage roll-off. Note the short channel effects degrade due to quantum tunneling, especially in the gate length of below 10nm, and DGMOSFETs have to be very strictly designed in the regime of below 10nm gate length since quantum tunneling becomes the main transport mechanism in the subthreshold region.

• Journal of the Korean Institute of Telematics and Electronics T
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• v.35T no.2
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• pp.6-12
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• 1998

Thin film SOI(Silicon-on-insulator) device offer unique advantages such as reduction in short channel effects, improvement of subthreshold slope, higher mobility, latch-up free nature, and so on. But these devices exhibit floating-body effet such as current kink which inhibits the proper device operation. In this paper, the SOI NMOSFET with a T-type gate structure is proposed to solve the above problem. To simulate the proposed device with TSUPREM-4, the part of gate oxide was considered to be 30nm thicker than the normal gate oxide. The I-V characteristics were simulated with 2D MEDICI. Since part of gate oxide has different oxide thickness, the gate electric field strength is not same throughout the gate and hence the impact ionization current is reduced. The current kink effect will be reduced as the impact ionization current drop. The reduction of current kink effect for the proposed device structure were shown using MEDICI by the simulation of impact ionization current, I-V characteristics, and hole current distribution.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.28 no.6
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• pp.365-370
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• 2015

Zinc tin oxide transparent thin film transistors (ZTO TTFTs) were fabricated on oxidized $n^+$ Si wafers. The thickness of ~30 nm $Al_2O_3$ films were deposited on the oxidized Si wafers by atomic layer deposition, which acted as the gate insulators of ZTO TTFTs. The $Al_2O_3$ films were rapid-annealed at $400^{\circ}C$, $600^{\circ}C$, $800^{\circ}C$, and $1,000^{\circ}C$, respectively. Active layers of ZTO films were deposited on the $Al_2O_3/SiO_2$ coated $n^+$ Si wafers by rf magnetron sputtering. Mobility and threshold voltage were measured as a function of the rapid-annealing temperature. X-ray photoelectron spectroscopy (XPS) were carried out to observe the chemical bindings of $Al_2O_3$ films. The annealing effects of gate-insulator on the properties of TTFTs were analyzed based on the results of XPS.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.19 no.9
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• pp.808-812
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• 2006

In this dissertation, Ru-Zr metal gate electrode deposited on two kinds of dielectric were formed for MOS capacitor. Sample co-sputtering method was used as a alloy deposition method. Various atomic composition was achieved when metal film was deposited by controlling sputtering power. To study the characteristics of metal gate electrode, C-V(capacitance-voltage) and I-V(current-voltage) measurements were performed. Work function and equivalent oxide thickness were extracted from C-V curves by using NCSU(North Carolina State University) quantum model. After the annealing at various temperature, thermal/chemical stability was verified by measuring the variation of effective oxide thickness and work function. This dissertation verified that Ru-Zr gate electrodes deposited on $SiO_{2}\;and\;ZrO_{2}$ have compatible work functions for NMOS at the specified atomic composition and this metal alloys are thermally stable. Ru-Zr metal gate electrode deposited on $SiO_{2}\;and\;ZrO_{2}$ exhibit low sheet resistance and this values were varied with temperature. Metal alloy deposited on two kinds of dielectric proposed in this dissertation will be used in company with high-k dielectric replacing polysilicon and will lead improvement of CMOS properties.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.3 no.2
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• pp.471-475
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• 1999

The metal plasma-etch damage immunity of nMOSFET with $N{_2}O$ gate oxide is found to be improved comparing to that with regular pure oxide of similar thickness. With increasing the antenna ratio (AR), the characteristics of nMOSFETs with $N{_2}O$ oxide shows tighter initial distribution and smaller degradation under constant field stress, which is explained by the effect of the nitrogen at the substrate $Si/SiO_2$ interface. Also, if $N{_2}O$ gate oxide is used, the maximum allowable size of metal AAR and PAR may be increased to the much larger values. These improvements of nMOSFETs with $N{_2}O$ gate oxide are attributed to the effect of the interface hardness improved by the nitrogen included at the substrate-Si/$N{_2}O$-oxide interface.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2002.11a
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• pp.163-166
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• 2002

We investigated structural and electrical properties of Metal-Oxide-Semiconductor(MOS) structure using Hafnium $oxide(HfO_{2})$ as high-k gate dielectric material. $HfO_{2}$ films are ultrathin gate dielectric material witch have a thickness less than 2.0nm， so it is spotlighted to be substituted $SiO_{2}$ as gate dielectric material. In this paper We have grown $HfO_{2}$ films with pt electrode on P-type Silicon substrate by RF magnetron sputtering system using $HfO_{2}$ target and oserved the property of semiconductor-oxide interface. Using pt electrode, it is necessary to be annealed at ${300^{\circ}C}$. This process is to increase an adhesion ratio between $HfO_{2}$ films with pt electrode. In film deposition process, the deposition time of $HfO_{2}$ films is an important parameter. Structura1 properties are invetigated by AES depth profile, and electrical properties by Capacitance-Voltage characteristic. Interface trap density are measured to observe the interface between $HfO_{2}$ with Si using High-frequency(1MHz) C-V and Quasi - static C-V characteristic.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.19 no.1
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• pp.163-168
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• 2015

This paper analyzed the deviation of tunneling current for bottom gate voltage of sub-10 nm asymmetric double gate MOSFET. The asymmetric double gate MOSFET among multi gate MOSFET developed to reduce the short channel effects has the advantage to increase the facts to be able to control the channel current, compared with symmetric double gate MOSFET. The increase of off current is, however, inescapable if aymmetric double gate MOSFET has the channel length of sub-10 nm. The influence of tunneling current was investigated in this study as the portion of tunneling current for off current was calculated. The tunneling current was obtained by the WKB(Wentzel-Kramers-Brillouin) approximation and analytical potential distribution derived from Poisson equation. As a results, the tunneling current was greatly influenced by bottom gate voltage in sub-10 nm asymmetric double gate MOSFET. Especially it showed the great deviation for channel length, top and bottom gate oxide thickness, and channel thickness.