• 센서학회지
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• 제25권5호
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• pp.320-325
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• 2016

In this paper, we propose an AlGaN/GaN-based extended-gate metal-insulator-semiconductor high electron mobility transistor (MISHEMT)-type biosensor for detecting streptavidin-biotin complexes. We measure the drain current of the fabricated sensor, which varies depending on the antibody-antigen reaction of streptavidin with biotin molecules. To confirm the immobilization of biotin polyethylene glycol (PEG) thiol, we analyze the Au surface of a GaN sample using X-ray photoelectron spectroscopy (XPS). The proposed biosensor shows higher sensitivity than Si-based extended-gate metal oxide semiconductor field effect transistor (MOSFET)-type biosensor. In addition, the proposed AlGaN/GaN-based extended-gate MISHEMT-type biosensor exhibits better long-term stability, compared to the conventional AlGaN/GaN-based MISHEMT-type biosensor.

• 한국재료학회:학술대회논문집
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• 한국재료학회 2008년도 춘계학술발표대회 및 제14회 신소재 심포지엄
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• pp.3.2-3.2
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• 2008

• JSTS:Journal of Semiconductor Technology and Science
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• 제1권1호
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• pp.31-39
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• 2001

W polymetal gate technology for giga bit DRAM are presented. Key module processes for polymetal gate are studied in detail. $W/WN_x/poly-silicon$ adopted for a word line of 256Mbit DRAM has good gate oxide integrity and junction leakage characteristics through full integration, which is comparable to those of conventional $WSi_x$/Poly-silicon gate process. These results undoubtedly show that $W/WN_x/poly-silicon$ is the strongest candidate as a word line for Giga bit DRAM.

• 한국재료학회:학술대회논문집
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• 한국재료학회 2012년도 춘계학술발표대회
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• pp.67.1-67.1
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• 2012

Graphene has attracted much attention for future nanoelectronics due to its superior electrical properties. Owing to its extremely high carrier mobility and controllable carrier density, graphene is a promising material for practical applications, particularly as a channel layer of high-speed FET. Furthermore, the planar form of graphene is compatible with the conventional top-down CMOS fabrication processes and large-scale synthesis by chemical vapor deposition (CVD) process is also feasible. Despite these promising characteristics of graphene, much work must still be done in order to successfully develop graphene FET. One of the key issues is the process technique for gate dielectric formation because the channel mobility of graphene FET is drastically affected by the gate dielectric interface quality. Formation of high quality gate dielectric on graphene is still a challenging. Dirac voltage, the charge neutral point of the device, also strongly depends on gate dielectrics. Another performance killer in graphene FET is source/drain contact resistance, as the contact resistant between metal and graphene S/D is usually one order of magnitude higher than that between metal and silicon S/D. In this presentation, the key issues on graphene-based FET, including organic-inorganic hybrid gate dielectric formation, controlling of Dirac voltage, reduction of source/drain contact resistance, device structure optimization, graphene gate electrode for improvement of gate dielectric reliability, and CVD graphene transfer process issues are addressed.

• JSTS:Journal of Semiconductor Technology and Science
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• 제11권4호
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• pp.278-286
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• 2011

In this paper, we present a compact model of gate-voltage-dependent quantum effects in short-channel surrounding-gate (SG) metal-oxide-semiconductor field-effect transistors (MOSFETs). We based the model on a two-dimensional (2-D) analytical solution of Poisson's equation using cylindrical coordinates. We used the model to investigate the electrostatic potential and current sensitivities of various gate lengths ($L_g$) and radii (R). Schr$\ddot{o}$dinger's equation was solved analytically for a one-dimensional (1-D) quantum well to include quantum effects in the model. The model takes into account quantum effects in the inversion region of the SG MOSFET using a triangular well. We show that the new model is in excellent agreement with the device simulation results in all regions of operation.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2003년도 추계학술대회 논문집 Vol.16
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• pp.15-18
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• 2003

Ta-Ti metal alloy is proposed for alternate gate electrode of ULSI MOS device. Ta-Ti alloy was deposited directly on $SiO_2$ by a co-sputtering method and good interface property was obtained. The sputtering power of each metal target was 100W. Thermal and chemical stability of the electrode was studied by annealing at $500^{\circ}C$ and $600^{\circ}C$ in Ar ambient. X-ray diffraction was measured to study interface reaction and EDX(energy dispersive X-ray) measurement was performed to investigate composition of Ta and Ti element. Electrical properties were evaluated on MOS capacitor, which indicated that the work function of Ta-Ti metal alloy was ${\sim}4.1eV$ compatible with NMOS devices. The measured sheet resistance of alloy was lower than that of poly silicon.

• 통합자연과학논문집
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• 제3권1호
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• pp.7-18
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• 2010

Ethylene-bridged silsesquioxane resins were synthesized from two monomers: 1,2-bis(trimethoxysilyl)ethane and methyltrimethoxysilane. The silsesquioxane thin films were spin-coated from the copolymerized resins on silicon wafer. Metal insulator metal (MIM), metal insulator semiconductor (MIS) devices were utilized to investigate the electrical properties of the copolymerized thin films. As the films were inserted as gate insulator in the OTFT devices, the field effect mobilitites were evaluated by employing Poly(3-hexylthiophene) (P3HT) as organic semiconductor, which shows that their dielectric properties and mobility values are dependent on the molecular structures and Si-OH concentration involving in the films.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2002년도 하계학술대회 논문집
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• pp.358-361
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• 2002

Self-aligned MOSFETS using a polysilicon gate are widely fabricated in silicon technology. The polysilicon layer acts as a mask for the source and drain implants and does as gate electrode in the final product. However, the usage of polysilicon gate as a self-aligned mask is restricted in fabricating SiC MOSFETS since the following processes such as dopant activation, ohmic contacts are done at the very high temperature to attack the stability of the polysilicon layer. A metal instead of polysilicon can be used as a gate material and even can be used for ohmic contact to source region of SiC MOSFETS, which may reduce the number of the fabrication processes. Co-formation process of metal-source/drain ohmic contact and gate has been examined in the 4H-SiC based vertical power MOSFET At low bias region (<20V), increment of leakage current after RTA was detected. However, the amount of leakage current increment was less than a few tens of ph. The interface trap densities calculated from high-low frequency C-V curves do not show any difference between w/ RTA and w/o RTA. From the C-V characteristic curves, equivalent oxide thickness was calculated. The calculated thickness was 55 and 62nm for w/o RTA and w/ RTA, respectively. During the annealing, oxidation and silicidation of Ni can be occurred. Even though refractory nature of Ni, 950$^{\circ}C$ is high enough to oxidize it. Ni reacts with silicon and oxygen from SiO$_2$ 1ayer and form Ni-silicide and Ni-oxide, respectively. These extra layers result in the change of capacitance of whole oxide layer and the leakage current

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2000년도 추계종합학술대회 논문집(2)
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• pp.41-44
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• 2000

Ultra large scale integrated circuit(ULSI) & complementary metal oxide semiconductor(CMOS) circuits require gate electrode materials such as meta] silicides, titanium-silicide for gate oxides. Many previous authors have researched the improvements sub-micron gate oxide quality. However, little has been done on the electrical quality and reliability of ultra thin gates. In this research, we recommend novel shallow trench isolation structure and two step TiSi$_{2}$ formation for sub 0.1${\mu}{\textrm}{m}$ gate oxide.

• JSTS:Journal of Semiconductor Technology and Science
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• 제4권1호
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• pp.1-11
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• 2004

A FinFET, a novel double-gate device structure is capable of scaling well into the nanoelectronics regime. High-performance CMOS FinFETs , fully depleted silicon-on-insulator (FDSOI) devices have been demonstrated down to 15 nm gate length and are relatively simple to fabricate, which can be scaled to gate length below 10 nm. In this paper, some of the key elements of these technologies are described including sub-lithographic pattering technology, raised source/drain for low series resistance, gate work-function engineering for threshold voltage adjustment as well as metal gate technology, channel roughness on carrier mobility, crystal orientation effect, reliability issues, process variation effects, and device scaling limit.