• Transactions on Electrical and Electronic Materials
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• v.5 no.5
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• pp.169-172
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• 2004

Deep sub-micron device required to get the superior ultra thin gate oxide characteristics. In this research, I will recommend a novel shallow trench isolation structure(STI) for thin gate oxide and a $N_2$O gate oxide 30 $\AA$ by NO ambient process. The local oxidation of silicon(LOCOS) isolation has been replaced by the shallow trench isolation which has less encroachment into the active device area. Also for $N_2$O gate oxide 30 $\AA$, ultra thin gate oxide 30 $\AA$ was formed by using the $N_2$O gate oxide formation method on STI structure and LOCOS structure. For the metal electrode and junction, TiSi$_2$ process was performed by RTP annealing at 850 $^{\circ}C$ for 29 sec. In the viewpoints of the physical characteristics of MOS capacitor, STI structure was confirmed by SEM. STI structure was expected to minimize the oxide loss at the channel edge. Also, STI structure is considered to decrease the threshold voltage, result in a lower Ti/TiN resistance( Ω /cont.) and higher capacitance-gate voltage(C- V) that made the STI structure more effective. In terms of the TDDB(sec) characteristics, the STI structure showed the stable value of 25 % ～ 90 % more than 55 sec. In brief, analysis of the ultra thin gate oxide 30 $\AA$ proved that STI isolation structure and salicidation process presented in this study. I could achieve improved electrical characteristics and reliability for deep submicron devices with 30 $\AA$ $N_2$O gate oxide.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2003.07a
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• pp.319-322
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• 2003

To match the charge induced by the insulators $CeO_2$ with the remanent polarization of ferro electric SBT thin films, areas of Pt/SBT/Pt (MFM) and those of $Pt/CeO_2/Si$ (MIS) capacitors were ind ependently designed. The area $S_M$ of MIS capacitors to the area $S_F$ of MFM capacitors were varied from 1 to 10, 15, and 20. Top electrode Pt and SBT layers were etched with for various area ratios of $S_M\;/\;S_F$. Bottom electrode Pt and $CeO_2$ layers were respectively deposited by do and rf sputtering in-situ process. SBT thin film were prepared by the metal orgnic decomposition (MOD) technique. $Pt(100nm)/SBT(350nm)/Pt(300nm)/CeO_2(40nm)/p-Si$ (MFMIS) gate structures have been fabricated with the various $S_M\;/\;S_F$ ratios using inductively coupled plasma reactive ion etching (ICP-RIE). The leakage current density of MFMIS gate structures were improved to $6.32{\times}10^{-7}\;A/cm^2$ at the applied gate voltage of 10 V. It is shown that in the memory window increase with the area ratio $S_M\;/\;S_F$ of the MFMIS structures and a larger memory window of 3 V can be obtained for a voltage sweep of ${\pm}9\;V$ for MFMIS structures with an area ratio $S_M\;/\;S_F\;=\;6$ than that of 0.9 V of MFS at the same applied voltage. The maximum memory windows of MFMIS structures were 2.28 V, 3.35 V, and 3.7 V with the are a ratios 1, 2, and 6 at the applied gate voltage of 11 V, respectively. It is concluded that ferroelectric gate capacitors of MFMIS are good candidates for nondestructive readout-nonvolatile memories.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2001.07a
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• pp.267-270
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• 2001

A new small scaling Lateral Trench Insulated Gate Bipolar Transistor (SSLTIGBT) was proposed to improve the characteristics of the device. The entire electrode of the LTIGBT was replaced with a trench-type electrode. The LTIGBT was designed so that the width of device was no more than 10$\mu\textrm{m}$. The latch-up current densities were improved by 4.5 and 7.6 times, respectively, compared to those of the same sifted conventional LTIGBT and the conventional LTIGBT which has the width of 17$\mu\textrm{m}$. The enhanced latch-up capability of the SSLTIGBT was obtained due to the fact that the hole current in the device reaches the cathode via the p+ cathode layer underneath the n+ cathode layer, directly. The forward blocking voltage of the SSLTIGBT was 125 V. At the same size, those of the conventional LTIGBT and the conventional LTIGBT with the width of 17$\mu\textrm{m}$ were 65 V and 105 V, respectively. Because the proposed device was constructed of trench-type electrodes, the electric field in the device were crowded to trench oxide. Thus, the punch through breakdown of LTEIGBT occurred late.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2008.11a
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• pp.12-12
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• 2008

Ruthenium is one of the noble metals having good thermal and chemical stability, low resistivity, and relatively high work function(4.71eV). Because of these good physical, chemical, and electrical properties, Ru thin films have been extensively studied for various applications in semiconductor devices such as gate electrode for FET, capacitor electrodes for dynamic random access memories(DRAMs) with high-k dielectrics such as $Ta_2O_5$ and (Ba,Sr)$TiO_3$, and capacitor electrode for ferroelectric random access memories(FRAMs) with Pb(Zr,Ti)$O_3$. Additionally, Ru thin films have been studied for copper(Cu) seed layers for Cu electrochemical plating(ECP) in metallization process because of its good adhesion to and immiscibility with Cu. We investigated Ru thin films by thermal ALD with various deposition parameters such as deposition temperature, oxygen flow rate, and source pulse time. Ru thin films were grown by ALD(Lucida D100, NCD Co.) using RuDi as precursor and $O_2$ gas as a reactant at 200~$350^{\circ}C$.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2009.06a
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• pp.331-331
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• 2009

Hafnium oxide ($HfO_2$) attracted by one of the potential candidates for the replacement of si-based oxides. For applications of the high-k gate dielectric material, high thermodynamic stability and low interface-trap density are required. Furthermore, the amorphous film structure would be more effective to reduce the leakage current. To search the gate oxide materials, metal-insulator-metal (MIM) capacitors was fabricated by pulsed laser deposition (PLD) on indium tin oxide (ITO) coated glass with different oxygen pressures (30 and 50 mTorr) at room temperature, and they were deposited by Au/Ti metal as the top electrode patterned by conventional photolithography with an area of $3.14\times10^{-4}\;cm^2$. The results of XRD patterns indicate that all films have amorphous phase. Field emission scanning electron microscopy (FE-SEM) images show that the thickness of the $HfO_2$ films is typical 50 nm, and the grain size of the $HfO_2$ films increases as the oxygen pressure increases. The capacitance and leakage current of films were measured by a Agilent 4284A LCR meter and Keithley 4200 semiconductor parameter analyzer, respectively. Capacitance-voltage characteristics show that the capacitance at 1 MHz are 150 and 58 nF, and leakage current density of films indicate $7.8\times10^{-4}$ and $1.6\times10^{-3}\;A/cm^2$ grown at 30 and 50 mTorr, respectively. The optical properties of the $HfO_2$ films were demonstrated by UV-VIS spectrophotometer (Scinco, S-3100) having the wavelength from 190 to 900 nm. Because films show high transmittance (around 85 %), they are suitable as transparent devices.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2008.11a
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• pp.149-149
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• 2008

Metal-Insulator-Metal(MIM) capacitors have been studied extensively for next generation of high-density dynamic random access memory (DRAM) devices. Of several candidates for metal electrodes, Ru or its conducting oxide $RuO_2$ is the most promising material due to process maturity, feasibility, and reliability. ALD can be used to form the Ru and RuO2 electrode because of its inherent ability to achieve high level of conformality and step coverage. Moreover, it enables precise control of film thickness at atomic dimensions as a result of self-limited surface reactions. Recently, ALD processes for Ru and $RuO_2$, including plasma-enhanced ALD, have been studied for various semiconductor applications, such as gate metal electrodes, Cu interconnections, and capacitor electrodes. We investigated Ru/$RuO_2$ thin films by thermal ALD with various deposition parameters such as deposition temperature, oxygen flow rate, and source pulse time. Ru and $RuO_2$ thin films were grown by ALD(Lucida D150, NCD Co.) using RuDi as precursor and O2 gas as a reactant at $200\sim350^{\circ}C$.

• Korean Journal of Crystallography
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• v.16 no.2
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• pp.89-101
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• 2005

Among many material processing related issues for successful scaling down of devices for the next 10 years or so, the advanced gate stack and interconnect technology are two most critical research areas, which need technical innovation. The introduction of new metallic films and appropriate processing technologies are required more than ever. Especially, as the device downscaling continues well into sub 50 nm regime, the paradigm for metal nano film deposition technique research has been shifted to high conformality, low growth temperature, high quality with uniformity at large area wafers. Regarding these, ALD has sparked a lot of interests for a number of reasons. The process is intrinsically atomic in nature, resulting in the controlled deposition of films in sub-monolayer units with excellent conformality. In this paper, the overview on the current issues and the future trends in device processing technologies related to metal nano films as well as the R&D trends in these applications will be discussed. The focus will be on the applications for metal gate, capacitor electrode for DRAM, and diffusion barriers/seed layers for Cu interconnect technology.

• Journal of Information Display
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• v.10 no.2
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• pp.54-61
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• 2009

The results of the optimization of the organic passivation process for fabricating thin-film transistors (TFTs) with a high aperture ratio on a seventh-generation glass (2200${\times}$1870 mm) substrate for LCD-TV panels are reported herein. The optimization of the organic passivation process has been verified by checking various factors, including the material properties (e.g., thickness, stain, etching, thermal reflow) and the effects on the TFT operation (e.g., gate/data line delay and display-driving properties). The two main factors influencing the organic passivation process are the optimization of the final thickness of the organic passivation layer, and the gate electrode. In conclusion, the minimum possible final thickness was found to be $2.42{\um}m$ via simulation and pilot testing, using the full-factorial design. The optimization of the organic passivation layer was accomplished by improving its brightness by over 10 cd/$m^2$ (ca. 2% luminance) compared to that of the conventional organic passivation process. The results of this research also help reduce the reddish stain on display panels.

• Transactions on Electrical and Electronic Materials
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• v.9 no.4
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• pp.169-172
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• 2008

We attempted to fabricate carbon nanotube field effect transistor (CNT-FET) using single walled carbon nanotube(SWNT) on the heavily doped Si substrate used as a bottom gate, source and drain electrode were fabricated bye-beam lithography on the 500 nm thick $SiO_2$ gate dielectric layer. We investigated electrical and physical properties of this CNT-FET using Scanning Probe Microscope(SPM) and conventional method based on tungsten probe tip technique. The gate length of CNT-FET was 600 nm and the diameter of identified SWNT was about 4 nm. We could observed gating effect and typical p-MOS property from the obtained $V_G-I_{DS}$ curve. The threshold voltage of CNT-FET is about -4.6V and transconductance is 47 nS. In the physical aspect, we could identified SWNT with phase mode of SPM which detecting phase shift by force gradient between cantilever tip and sample surface.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.15 no.9
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• pp.750-757
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• 2002

A new lateral trench LTEIGBT with p+ diverter was proposed to suppress latch-up of LTIGBT The p+ diverter was placed between the anode and cathode electrode. The latch-up of LTEICBT with a p+ diverter was effectively suppressed to sustain an anode voltage of 8.7V and a current density of 1453A/$\textrm{cm}^2$ while in the conventional LTIGBT, latch-up occured at an anode current density of 540A/$\textrm{cm}^2$. In addition, the forward blocking voltage of the proposed LTEIGBT with a p+ diverter was about 140V. The forward blocking voltage of the conventional LTIGBT of the same size was no more than 105V, We fabricated the proposed LTEIGBT with a p+ diverter after the device and process simulation was finished. When the gate voltage is applied 12V, the forward conduction currents of the proposed LTEIGBT with a p+ diverter and the conventional LIGBT are 90㎃ and 70㎃, respectively, at the same breakdown voltage of 150V.