• Proceedings of the Materials Research Society of Korea Conference
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• 2012.05a
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• pp.67.1-67.1
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• 2012

Graphene has attracted much attention for future nanoelectronics due to its superior electrical properties. Owing to its extremely high carrier mobility and controllable carrier density, graphene is a promising material for practical applications, particularly as a channel layer of high-speed FET. Furthermore, the planar form of graphene is compatible with the conventional top-down CMOS fabrication processes and large-scale synthesis by chemical vapor deposition (CVD) process is also feasible. Despite these promising characteristics of graphene, much work must still be done in order to successfully develop graphene FET. One of the key issues is the process technique for gate dielectric formation because the channel mobility of graphene FET is drastically affected by the gate dielectric interface quality. Formation of high quality gate dielectric on graphene is still a challenging. Dirac voltage, the charge neutral point of the device, also strongly depends on gate dielectrics. Another performance killer in graphene FET is source/drain contact resistance, as the contact resistant between metal and graphene S/D is usually one order of magnitude higher than that between metal and silicon S/D. In this presentation, the key issues on graphene-based FET, including organic-inorganic hybrid gate dielectric formation, controlling of Dirac voltage, reduction of source/drain contact resistance, device structure optimization, graphene gate electrode for improvement of gate dielectric reliability, and CVD graphene transfer process issues are addressed.

• Transactions on Electrical and Electronic Materials
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• v.2 no.3
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• pp.33-37
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• 2001

A vertical trench electrode type EST has been proposed in this paper. The proposed device considerably improves snapback which leads to a lot of problems of device applications. In this paper, the vertical dual gate Emitter Switched Thyristor (EST) with trench electrode has been proposed for improving snab-back effect. It is observed that the forward blocking voltage of the proposed device is 745V. The conventional EST of the same size were no more than 633V. Because the proposed device was constructed of trench-type electrodes, the electric field moved toward trench-oxide layer, and the punch through breakdown of the proposed EST is occurred at latest.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 1999.05a
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• pp.473-476
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• 1999

PMOS capacitors with Ce-policide electrode were fabricated by the SADS method to study the effects of activation condition on the C-V characteristics. For the activation temperature of $600^{\circ}C$ , the capacitor using CoSi$_2$ formed from Co/Ti bilayer as diffusion source showed excellent C-V properties and the increase in V$_{th}$ with the increasing activation time. But impurties into the oxide.e.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2002.07a
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• pp.342-345
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• 2002

A new lateral trench electrode IGBT with p+ diverter was Proposed to suppress latch-up of LTIGBT. The p+ diverter was placed between the anode and cathode electrode. The latch-up of LTEIGBT with a p+ diverter was effectively suppressed to sustain an anode voltage of 8.7V and a current density of 1453A/$\textrm{cm}^2$ while in the conventional LTIGBT, latch-up occurred at an anode current density of 540A/$\textrm{cm}^2$. And the forward blocking voltage of the proposed LTEIGBT with a p+ diverter was about 140V. That of the conventional LTIGBT of the same size was no more than 105V. When the gate voltage is applied 12V, the forward conduction currents of the Proposed LTEIGBT with a p+ diverter and the conventional LIGBT are 90mA and 70mA, respectively, at the same breakdown voltage of 150V.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.29 no.2
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• pp.69-74
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• 2016

In this study, we proposed an a-IGZO (amorphous In-Ga-Zn-O) TFT (thin-film transistor) with off-planed source/drain structure. Furthermore, two different electrode materials (ITO and Ti) were applied to the source and drain contacts for performance improvement of a-IGZO TFTs. When the ITO with a large work-function and the Ti with a small work-function are applied to drain electrode and source contact, respectively, the electrical performances of a-IGZO TFTs were improved; an increased driving current, a decreased leakage current, a high on-off current ratio, and a reduced subthreshold swing. As a result of gate bias stress test at various temperatures, the off-planed S/D a-IGZO TFTs showed a degradation mechanism due to electron trapping and both devices with ITO-drain or Ti-drain electrode revealed an equivalent instability.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.24 no.12
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• pp.988-991
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• 2011

We fabricated a copper phthalocyanine (CuPc) based field-effect transistor with different device structure as a bottom and top contact FET. Also, we used a $SiO_2$ as a gate insulator and analyzed using a current-voltage (I-V) characteristics of the bottom and top contact CuPc FET device. In order to discuss the channel formation, we were observed the capacitance-gate voltage(C-V) characteristics of the bottom and top contact CuPc FET device.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.17 no.4
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• pp.426-431
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• 2004

We have studied the pressure-dependent liquid crystal's dynamics in a twisted nematic (TN) liquid crystal panel with thin film transistor by applying an external pressure to it. When the external pressure is applied to the panel in a dark state, the disclination lines were generated as a light leakage whereas they did not appear in a simple test cell that has only pixel and common electrodes. It was because the disclination lines were Provoked by the electric field between pixel electrode and data/gate bus line for active matrix driving. Consequently, the external pressure resulted in dynamic instability of the liquid crystal so that the disclination lines at the data/gate bus line intruded into the active area.

• Transactions on Electrical and Electronic Materials
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• v.4 no.3
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• pp.34-37
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• 2003

[ $HfO_2$ ] and $HfO_xN_y$ films were deposited by plasma-enhanced chemical vapor deposition using $Hf[OC(CH_3)_3]_4$ as the precursor in the absence of $O_2$. The crystallization temperature of the $HfO_xN_y$ films is higher than that of the $HfO_2$ film. Nitrogen incorporation in $HfO_xN_y$ was confirmed by auger electron spectroscopy analysis. After post deposition annealing (PDA) at 800$\Box$, the EOT increased from 1.34 to 1.6 nm in the $HfO_2$ thin films, whereas the increase of EOT was suppressed to less than 0.02 nm in the $HfO_xN_y$. The leakage current density decreased from 0.18 to 0.012 $A/cm^2$ with increasing PDA temperature in the $HfO_2$ films. But the leakage current density of $HfO_xN_y$ does not vary with increasing PDA temperature because an amorphous $HfO_xN_y$ films suppresses the diffusion of oxygen through the gate dielectric.

• Transactions on Electrical and Electronic Materials
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• v.4 no.2
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• pp.15-19
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• 2003

In this paper, the new dual trench gate Emitter Switched Thyristor (DTG-EST) is proposed for improving snap-back effect which leads to a lot of serious problems of device applications. Also the parasitic thyristor that is inherent in the conventional EST is completely eliminated in this structure, allowing higher maximum controllable current densities for ESTs. The conventional EST exhibits snap-back with the anode voltage and current density 2.73V and 35A/$\textrm{cm}^2$, respectively. But the proposed DTG-EST exhibits snap-back with the anode voltage and current density 0.96V and 100A/$\textrm{cm}^2$, respectively.

• Proceedings of the Korean Vacuum Society Conference
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• 2013.02a
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• pp.653-653
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• 2013

In this study, ITO extended gate reduced graphene oxide field effect transistor (rGO FET) was demonstrated as a transducer for a proton sensing application. In this structure, the sensing area is isolated from the active area of the device. Therefore, it is easy to deposit or modify the sensing area without affecting on the device performance. In this case, the ITO extended gate was used as a gate electrode as well as a proton sensing material. The proton sensing properties based on the rGO FET transducer were analyzed. The rGO FET device showed a high stability in the air ambient with a TTC encapsulation layer for months. The device showed an ambipolar characteristic with the Dirac point shift with varying the pH solutions. The sensing characteristics have offered the potential for the ion sensing application.