• 전자공학회논문지
• /
• 제52권2호
• /
• pp.112-118
• /
• 2015

기존의 동기방식의 회로는 나노미터 영역에서의 공정, 전압, 온도 변이 (PVT variation), 그리고 노화의 영향으로 시스템의 전체 성능을 유지할 수 없을 뿐만 아니라 올바른 동작을 보장할 수도 없다. 따라서 본 논문에서는 여러 가지 변이에 영향을 받지 않는 비동기회로 설계 방식 중에서 타이밍 분석이 요구되지 않고, 설계가 간단한 DI(delay insentive) 방식의 NCL (Null Convention Logic) 설계 방식을 이용하여 디지털 시스템을 설계하고자 한다. 기존의 NCL 게이트들의 회로 구조들은 느린 스피드, 높은 영역 오버헤드, 높은 와이어(wire) 복잡도와 같은 약점을 가지고 있기 때문에 본 논문에서는 빠른 스피드, 낮은 영역 오버헤드, 낮은 와이더 복잡도를 위해서 트랜지스터 레벨에서 설계된 새로운 저전력 고속 NCL 게이트 라이브러리를 제안하고자 한다. 제안된 NCL 게이트들은 동부 0.11um 공정으로 구현된 비동기 방식의 곱셈기의 지연, 소모 전력에 의해서 기존의 NCL 게이트 들과 비교되었다.

• 한국정보과학회논문지:시스템및이론
• /
• 제31권8호
• /
• pp.453-464
• /
• 2004

In order to solve the well-known drawback of reduced flexibility that is associate with ASIC implementations, this paper proposes a novel arithmetic unit over GF(2$^{m}$ ) for field programmable gate arrays (FPGAs) implementations of elliptic curve cryptographic processor. The proposed arithmetic unit is based on the binary extended GCD algorithm and the MSB-first multiplication scheme, and designed as systolic architecture to remove global signals broadcasting. The proposed architecture can perform both division and multiplication in GF(2$^{m}$ ). In other word, when input data come in continuously, it produces division results at a rate of one per m clock cycles after an initial delay of 5m-2 in division mode and multiplication results at a rate of one per m clock cycles after an initial delay of 3m in multiplication mode respectively. Analysis shows that while previously proposed dividers have area complexity of Ο(m$^2$) or Ο(mㆍ(log$_2$$^{m}$ )), the Proposed architecture has area complexity of Ο(m), In addition, the proposed architecture has significantly less computational delay time compared with the divider which has area complexity of Ο(mㆍ(log$_2$$^{m}$ )). FPGA implementation results of the proposed arithmetic unit, in which Altera's EP2A70F1508C-7 was used as the target device, show that it ran at maximum 121MHz and utilized 52% of the chip area in GF(2$^{571}$ ). Therefore, when elliptic curve cryptographic processor is implemented on FPGAs, the proposed arithmetic unit is well suited for both division and multiplication circuit.

• ETRI Journal
• /
• 제7권4호
• /
• pp.11-14
• /
• 1985

바이폴라 소자로 구성된 회로가 양호한 특성을 갖기 위해서는 개별 소자의 동작 속도, 집적도 및 전력 소비 특성이 좋아야 한다. 그런데 지금까지 주로 사용해온 기존의 SBC 바이폴라 트랜지스터로는 이들 특성을 개선하는 데는 한계가 있었다. 일반적으로 바이폴라 트랜지스터는 면적이 줄어듦에 따라 이들 특성이 개선되므로 본 연구에서는 SBC 방법과는 다른 PSA 공정 방법을 개발하였다. 즉, 소자 격리에서의 종래의 PN 접합에 의한 방법과 다른 산화막에 의한 방법을 도입하였고 또한 에미터, 베이스 사이의 거리를 최소로 줄이기 위하여 다결정 실리콘에 의한 polysilicon self-align 방법으로 에미터 및 베이스를 형성시켰다.

• 전자공학회논문지SC
• /
• 제39권2호
• /
• pp.140-145
• /
• 2002

본 논문은 단락회로 전류를 없애기 위한 CMOS 버퍼회로에 대한 것이다. 최종 구동소자는 풀-업 PMOS와 풀-다운 NMOS로 구성하고 이를 구동하기 위해 두가지 경로를 입력신호로 선택되도록 하였다. 이러한 기법으로 최종 구동회로가 짧은 시간동안 tri-state가 되어 단락회로 전류를 차단하였다. 모의 실험결과 전원전압 3.3V에서 전력-지연 곱을 기존의 Tapered 버퍼[1]와 비교하여 약 42% 줄일 수 있었다

• IEIE Transactions on Smart Processing and Computing
• /
• 제5권3호
• /
• pp.199-206
• /
• 2016

This paper describes a simple routing control system. We propose achieving high-speed data transmission without modifying the data frame configuration. To add a routing control signal, called the "labeling signal" in this paper, to the data frame, we use a frequency modulation technique on the transmitted frame. This means you need not change the data frame when you transmit additional signals. Using a prototype system comprising a field-programmable gate array and discrete elements, we investigate the system performance and devise a method to achieve high resolution. A three-channel routing control for a 10 Gb/s data frame was achieved, which confirms the advantages of the proposed system.

• 한국지능시스템학회:학술대회논문집
• /
• 한국퍼지및지능시스템학회 2003년도 ISIS 2003
• /
• pp.154-157
• /
• 2003

In order for testing faults of combinatorial logic circuit, the authors have developed a new diagnosis method: "Neural Network (NN) fault diagnosis", based on fm error back propagation functions. This method has proved the capability to test gate faults of wider range including so called SSA (single stuck-at) faults, without assuming neither any set of test data nor diagnosis dictionaries. In this paper, it is further shown that what kind of fault models can be detected in the NN fault diagnosis, and the simply modified one can extend to test delay faults, e.g. logic hazard as long as the delays are confined to those due to gates, not to signal lines.

• International Journal of Fuzzy Logic and Intelligent Systems
• /
• 제2권2호
• /
• pp.146-152
• /
• 2002

Mold level control has been a major control task for continuous casting plants. The system involves nonlinearities such as stick-slip friction in the sliding gate, time-delay, friction force variations between molten steel and the inner wall of mold, and nozzle logging/unclogging. These complex problems should be solved to control mold level for steel cast. In this paper, we propose a neural fuzzy mold level control technique for solving these complex problems and give experiment studies to show the mold level control in continuous casting process.

• 한국정보과학회:학술대회논문집
• /
• 한국정보과학회 2003년도 봄 학술발표논문집 Vol.30 No.1 (B)
• /
• pp.283-285
• /
• 2003

We have developed an optimization algorithm based formulation for performing efficient time driven simultaneous place and route for FPGAS. Field programmable gate array(FPGAS) provide of drastically reducing the turn-around time for digital ICs, with a relatively small degradation in performance. For a variety of application specific Integrated circuit application, where time-to-market is most critical and the performance requirement do not mandate a custom or semicustom approach, FPGAS are an increasingly popular alternative. This has prompted a substantial amount of specialized synthesis and layout research focused on maximizing density, minimizing delay, and minimizing design time.

• 한국정보전자통신기술학회논문지
• /
• 제11권3호
• /
• pp.270-276
• /
• 2018

This paper presents a low area 256-point pipelined FFT architecture, especially for IEEE 802.16a WiMAX systems. Radix-24 algorithm and single-path delay feedback (SDF) architecture are adopted in the design to reduce the complexity of twiddle factor multiplication. A new cascade canonical signed digit (CSD) complex multipliers are proposed for twiddle factor multiplication, which has lower area and less power consumption than conventional complex multipliers composed of 4 multipliers and 2 adders. Also, the proposed cascade CSD multipliers can remove look-up table for storing coefficient of twiddle factors. In hardware implementation with Cyclone 10LP FPGA, it is shown that the proposed FFT design method achieves about 62% reduction in gate count and 64% memory reduction compared with the previous schemes.

• Journal of Power Electronics
• /
• 제14권6호
• /
• pp.1139-1146
• /
• 2014

Digital signal processor (DSP) and field programmable gate array (FPGA) based concentrated control systems are designed for implementing CPS-SPWM strategies. The self-defined universal asynchronous receiver/transmitter (UART) protocol is used for communication between a master controller and an individual module controller via high speed links. Aimed at undesired pulse competition, this paper analyzes its generation mechanism and presents a new method for eliminating competition pulses with no time delay. Finally, the proposed concentrated controller is applied to a 10kV/10MVar distribution static synchronous compensator (DSTATCOM) industrial prototype. Experimental results show the accuracy and reliability of the concentrated controller, and verify the superiority of the proposed elimination method for competition pulses.