Journal of the Institute of Electronics Engineers of Korea SC (전자공학회논문지SC)

The Institute of Electronics and Information Engineers (대한전자공학회)
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(A New CMOS Buffer for Low Power with Self-Controlled Dual Driving Path)

자기조정 이중구동 경로를 가진 새로운 저전력 CMOS 버퍼

  • 배효관 (동원대학 전자과) ;
  • 류범선 (충북대학교 전기전자공학과) ;
  • 조태원 (충북대학교 전기전자공학과)
  • Published : 2002.03.01
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Abstract

A new CMOS buffer removing short-circuit power consumption is proposed. The gate-driving signal of the pull-up(pull-down) transistor at the output is controlled by delayed internal signal to get tri-state output momentarily by shunting off the path of the short-circuit current. The SPICE simulation results verified the operation of the proposed buffer and showed the enhancement of the power-delay product at 3.3V supply voltage about 42% comparing to the conventional tapered CMOS buffer(1).

본 논문은 단락회로 전류를 없애기 위한 CMOS 버퍼회로에 대한 것이다. 최종 구동소자는 풀-업 PMOS와 풀-다운 NMOS로 구성하고 이를 구동하기 위해 두가지 경로를 입력신호로 선택되도록 하였다. 이러한 기법으로 최종 구동회로가 짧은 시간동안 tri-state가 되어 단락회로 전류를 차단하였다. 모의 실험결과 전원전압 3.3V에서 전력-지연 곱을 기존의 Tapered 버퍼[1]와 비교하여 약 42% 줄일 수 있었다

Keywords

References

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