• 한국정보디스플레이학회:학술대회논문집
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• 2006.08a
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• pp.1701-1703
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• 2006

Here we describe a novel driving scheme in the form of negative AC bias stress (NAC) to compensate shift in the threshold voltage for hydrogenated amorphous silicon (${\alpha}$-Si:H) thin film transistor (TFT) for AMOLED applications. This scheme preserves the threshold voltage shift of ${\alpha}$-Si:H TFT for infinitely long duration of time(>30,000 hours) and thereby overall performance, without using any additional TFTs for compensation. We briefly describe about the possible driving schemes in order to implement for real time AMOLED applications. We attribute most of the results based on concept of plugging holes and electrons across the interface of the gate insulator in a controlled manner.

• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.9
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• pp.55-59
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• 2013

A new method using RF Ids determined from measured S-parameters is proposed to extract the gate-voltage dependent effective carrier velocity of bulk MOSFETs in the saturation region without additional dc Ids measurement data suffering parasitic resistance effect that becomes larger with continuous down-scaling to sub-$0.1{\mu}m$. This method also allows us to extract the carrier velocity in the saturation region without the difficult extraction of bias-dependent parasitic gate-source capacitance and effective channel length. Using the RF technique, the electron velocity overshoot exceeding the bulk saturation velocity is observed in bulk N-MOSFETs with a polysilicon gate length of $0.065{\mu}m$.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.25 no.6
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• pp.409-413
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• 2012

In this study, a substrate-bias assisted 2-step pulse programming method is proposed for realizing 4-bit/1-cell operation of the SONOS memory. The programming voltage and time are considerably reduced by this programming method than a gate-bias assisted 2-step pulse programming method and CHEI method. It is confirmed that the difference of 4-states in the threshold voltage is maintained to more than 0.5 V at least for 10-year for the multi-level characteristics.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.42 no.2 s.332
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• pp.87-92
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• 2005

In this paper, adaptive bias circuit and PBG structure have been employed to suppress IMD and improve PAE (Power Added Efficiency) of the power amplifier. It is controlling the gate 'dc' bias voltage with the envelope of the input RF signal. and The PBG structure has been employed on the output port of power amplifier . The proposed power amplifier using adaptive bias circuit and PBG has been improved the IMG by 3 dBc, and the average PAE by $35.54\%$, respectively.

• JSTS:Journal of Semiconductor Technology and Science
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• v.15 no.5
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• pp.526-532
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• 2015

We quantitatively investigated instability mechanisms under simultaneous positive gate and drain bias stress (SPGDBS) in self-aligned top-gate amorphous indium-zinc-oxide thin-film transistors. After SPGDBS ($V_{GS}=13V$and $V_{DS}=13V$), the parallel shift of the transfer curve into a negative $V_{GS}$ direction and the increase of on current were observed. In order to quantitatively analyze mechanisms of the SPGDBS-induced negative shift of threshold voltage (${\Delta}V_T$), we experimentally extracted the density-of-state, and then analyzed by comparing and combining measurement data and TCAD simulation. As results, 19% and 81% of ${\Delta}V_T$ were taken to the donor-state creation and the hole trapping, respectively. This donor-state seems to be doubly ionized oxygen vacancy ($V{_O}^{2+}$). In addition, it was also confirmed that the wider channel width corresponds with more negative ${\Delta}V_T$. It means that both the donor-state creation and hole trapping can be enhanced due to the increase in self-heating as the width becomes wider. Lastly, all analyzed results were verified by reproducing transfer curves through TCAD simulation.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.5 no.1
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• pp.157-165
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• 2001

We analyzed the electrical characteristics of platinum silicide schottky junction to develope the voltage swing in Integrated Schottky Logic gates, and simulated the characteristics with the programs in this junctions. Simulation programs for analytic characteristics are the Medichi tool for device structure, Matlab for modeling and SUPREM V for fabrication process. The silicide junctions consist of PtSi and variable silicon substrate concentrations in ISL gates. Input parameters for simulation characteristics were the same conditions as process steps of the device farications process. The analitic electrical characteristics were the turn-on voltage, saturation current, ideality factor in forward bias, and has shown the results of breakdown voltage between actual characteristics and simulation characteristics in reverse bias. As a result, the forward turn-on voltage, reverse breakdown voltage, barrier height were decreased but saturation current and ideality factor were increased by substrates increased concentration variations.

• JSTS:Journal of Semiconductor Technology and Science
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• v.12 no.4
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• pp.473-481
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• 2012

For a mesa-isolated small geometry SOI MOSFET, the potentials in the silicon film, front, back, and side-wall oxide layers can be derived three-dimensionally. Using Taylor's series expansions of the trigonometric functions, the derived potentials are written in terms of the natural length that can be determined by using the derived formula. From the derived 3-D potentials, the minimum values of the front and the back surface potentials are derived and used to obtain the closed-form expressions for the front and back gate threshold voltages as functions of various device parameters and applied bias voltages. Obtained results can be found to explain the drain-induced threshold voltage roll-off and the narrow width effect of a fully depleted small geometry SOI MOSFET in a unified manner.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.20 no.2
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• pp.106-112
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• 2007

Advanced back-end processing requires the integration of low-k dielectrics and Cu. However, in the presence of an electric field and a temperature, positive Cu ions may drift rapidly through dielectric and causing reliability problems. Therefore, in this paper, Cu+ drift diffusion in two low-k materials and silicon oxide is evaluated. The drift diffusion is investigated by measuring shifts in the flat band voltage of capacitance-voltage measurements on Cu gate capacitors after bias thermal stressing. The Cu+ drift late in $SiO_{x}C_{y}\;(2.85{\pm}0.03)$ and Polyimide(2.7${\leq}k{\leq}3.0$) is Considerably lower than in thermal oxide.

• Proceedings of the KIEE Conference
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• 1987.07a
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• pp.775-778
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• 1987

Double-diffused metal oxide power semiconductor field effect transistors are used extensively in recent years in various circuit applications. The temperature variation of the drain current at a fixed bais shows both positive and negative resistance characteristics depending on the gate threhold voltage and gate-to source bias voltage. In this study, the decision method of the internal temperature measurement by $V_{GS}$ and $V_{DS}$ are presented.

• Journal of Information Display
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• v.6 no.4
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• pp.6-10
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• 2005

The dependence of hysteresis characteristics in low temperature poly-Si (LTPS) thin film transistors (TFTs) on the gate-source voltage (Vgs) or the drain-source voltage (Vds) bias is investigated and discussed. The hysteresis levels in both p-type and n-type LTPS TFTs are independent of Vds bias but increase as the sweep range of Vgs increases. It has been found that the hysteresis in both p-type and n-type LTPS TFTs originated from charge trapping and de-trapping in the channel region rather than at the source/drain edges.