• 대한전자공학회논문지SD
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• 제41권3호
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• pp.1-8
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• 2004

본 연구에서는 소오스와 드레인 근처에 포켓형상으로 이온이 주입되어 halo구조를 갖고 있는 MOSFET 소자의 1/f 잡음 특성에 대하여 고찰하였다. 채널 방향으로 전도도가 균일하지 않은 MOSFET 소자가 선형영역에서 동작할 때, 영역구분 근사기법(regional approach)을 근간으로 논의된 기존의 1/f 잡음모델을 영역별로 서로 다른 전기적 성질이 정의될 수 있는 halo MOSFET 소자에 적용하여 그 타당성을 조사하였다. 잡음모델의 검증을 위하여 기존의 모델에서와 같이 영역구분 근사를 사용하여 보다 넓은 동작범위에서 적용될 수 있도록 기존의 모델식을 개선하였다. 개선된 잡음식은 선형영역에서 기존에 보고된 잡음식에 수렴한다. 실험적으로 측정된 1/f 잡음 특성과의 비교에서 영역구분 근사기법으로 정리된 잡음식은 게이트 전압이 비교적 큰 경우에 한해서 적용될 수 있음을 보였다.

• 한국정보디스플레이학회:학술대회논문집
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• 한국정보디스플레이학회 2006년도 6th International Meeting on Information Display
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• pp.747-751
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• 2006

The hydrogenated amorphous silicon thin film transistor (a-Si:H TFT) with copper as source and drain electrode has been fabricated to obtain its transfer characteristics and stressed with positive and negative bias to investigate the instability variation comparing to conventional MoW-Al based TFT device. The results show that there is no copper diffusion into active layer of a-Si:H TFT, even during the thermal process. In addition, a 15-inch XGA a Si:H TFT LCD display utilizing Cu as gate electrodes has been developed.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2007년도 Techno-Fair 및 추계학술대회 논문집 전기물성,응용부문
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• pp.79-80
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• 2007

A high performance organic phototransistor with dynamic range of 120 dB is demonstrated by employing soluble pentacene as a photo-sensing layer. The organic phototransistor used suspended source/drain (SSD) electrode structure, which provides a dark current level of ${\sim}10^{-14}$ A at positive gate bias. Under a steady-state illumination, the organic phototransistor exhibited a current modulation of $10^6$ compared to dark to give a dynamic range of 120 dB. These results suggest that the organic phototransistor based on TIPS pentacene can be a new premising candidate for low-cost and high-performance photo-sensing element for digital imaging applications.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2006년도 하계학술대회 논문집 Vol.7
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• pp.467-468
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• 2006

We report on the fabrication of P3HT-based thin-film transistors (TFT) that consist of indium-zinc-oxide (IZO), PVP (poly-vinyl phenol), and Ni for the source-drain (S/D) electrode, gate dielectric, and gate electrode, respectively. The IZO S/D electrodes of which the work function is well matched to that of P3HT were deposited on a P3HT channel by thermal evaporation of IZO and showed a moderately low but still effective transmittance of ~25% in the visible range along with a good sheet resistance of ${\sim}60{\Omega}/{\square}$. The maximum saturation current of our P3HT-based TFT was about $15{\mu}A$ at a gate bias of -40V showing a high field effect mobility of $0.05cm^2/Vs$ in the dark, and the on/off current ratio of our TFT was about $5{\times}10^5$. It is concluded that jointly adopting IZO for the S/D electrode and PVP for gate dielectric realizes a high-quality P3HT-based TFT.

• 전자공학회논문지A
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• 제33A권10호
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• pp.123-129
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• 1996

LDD structure is widely accepted in fabricating short channel MOSFETs due to reduced short channel effect originated form lower drain edge electric field. However, modeling of the LDD device is troublesome because the analysis methods of LDD region known are either too complicated or inaccurate. To solve the problem, this paper presents a nonlinear resistance model for the LDD region based on teh fact that the electron mobility changes with positive gate bias because accumulation layer of electrons is formed at the surface of the LDD region. To prove the usefulness of the model, single source/drain and LDD nMOSFETs were fabricated with 0.35$\mu$m CMOS technolgoy. For the fabricated devices we have measured I$_{ds}$-V$_{gs}$ characteristics and compare them to the modeling resutls. First of all, we calculated channel and LDD region mobility from I$_{ds}$-V$_{gs}$ characteristics of 1050$\AA$ sidewall, 5$\mu$m channel length LDD NMOSFET. Then we MOSFET and found good agreement with experiments. Next, we use calculated channel and LDD region mobility to model I$_{ds}$-V$_{gs}$ characteristics of LDD mMOSFET with 1400 and 1750$\AA$ sidewall and 5$\mu$m channel length and obtained good agreement with experiment. The single source/drain device characteristic modeling results indicates that the cahnnel mobility obtained form our model in LDD device is accurate. In the meantime, we found that the LDD region mobility is governed by phonon and surface roughness scattering from electric field dependence of the mobility. The proposed model is useful in device and circuit simulation because it can model LDD device successfully even though it is mathematically simple.

• 한국전기전자재료학회논문지
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• 제31권6호
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• pp.372-376
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• 2018

The effects of off-state bias stress on the characteristics of p-type poly-Si TFT were investigated. To reduce the gate-induced drain leakage (GIDL) current, the off-state bias stress was changed by varying Vgs and Vds. After application of the off-state bias stress, the Vgs causing GIDL current was dramatically increased from 1 to 10 V, and thus, the Vgs margin to turn off the TFT was improved. The on-current and subthreshold swing in the aged TFT was maintained. We performed a technology computer-aided design (TCAD) simulation to describe the aged characteristics. The aged-transfer characteristics were well described by the local charge trapping. The activation energy of the GIDL current was measured for the pristine and aged characteristics. The reduced GIDL current was mainly a thermionic field-emission current.

• 한국통신학회논문지
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• 제35권1A호
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• pp.80-86
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• 2010

본 논문은 게이트 채널 길이 0.13 [${\mu}m$]의 p-MOS 트랜지스터에서 음 바이어스 온도 불안정(NBTI) 전류 스트레스 인가에 의한 게이트유기 드레인 누설(GIDL) 전류를 측정 분석하였다. NBTI 스트레스에 의한 문턱전압의 변화와 문턱전압아래 기울기와 드레인 전류 사이에 상관관계로부터, 소자의 특성 변화의 결과로 열화에 대한 중요한 메카니즘이 계면 상태의 생성과 관련이 있다는 것을 분석하였다. GIDL 전류의 측정 결과로부터, NBTI 스트레스에 기인한 계면상태에서 전자-정공 쌍의 생성이 GIDL 전류의 증가의 결과를 도출하였다. 이런 결과로 부터, 초박막 게이트 산화막 소자에서 NBTI 스트레스 후에 증가된 GIDL 전류를 고려해야만 한다. 또한, 동시에 신뢰성 특성과 직류 소자 성능의 고려가 나노 크기의 CMOS 통신회로 설계의 스트레스 파라미터들에서 반드시 있어야 한다.

• 한국정보통신학회논문지
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• 제18권5호
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• pp.1149-1154
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• 2014

본 연구는 산화물반도체트랜지스터의 터널링 현상을 살펴보기 위해서 게이트 절연막으로서 SiOC 박막을 사용하고 채널층으로 IGZO를 이용하여 트랜지스터를 제작 하였다. SiOC 박막은 분극이 작아질수록 비정질특성이 우수해지면서 절연특성이 좋아진다. SiOC 게이트 절연막과 채널 층 사이의 계면에 존재하는 접합특성은 SiOC의 분극특성에 따라서 달려졌다. 드레인소스 전류($I_{DS}$)와 게이트소스 전압($V_{GS}$)의 전달특성은 분극이 낮은 SiOC를 사용할 경우 양방향성 전달특성이 나타나고 분극이 높은 SiOC 게이트 절연막을 사용할 경우 단방향성 전달 특성이 나타났다. 터널링에 의한 양방향성 트랜지스터의 경우 바이어스 인가 전압이 낮은 ${\pm}1V$의 영역에서 쇼키접합을 나타냈었지만 트래핑효과에 의한 단방향성 트랜지스터의 경우 오믹접합 특성을 나타내었다. 특히 양방향성 트랜지스터의 경우 터널링 현상에 의하여 on/off 스위칭 특성이 개선되었다.

• JSTS:Journal of Semiconductor Technology and Science
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• 제6권1호
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• pp.22-29
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• 2006

We demonstrate highly manufacturable Multi-channel Field Effect Transistor (McFET) on bulk Si wafer. McFET shows excellent transistor characteristics, such as $5{\sim}6 times higher drive current than planar MOSFET, ideal subthreshold swing, low drain induced barrier lowering (DIBL) without pocket implantation and negligible body bias dependency, maintaining the same source/drain resistance as that of a planar transistor due to the unique feature of McFET. And suitable threshold voltage ($V_T$) for SRAM operation and high static noise margin (SNM) are achieved by using TiN metal gate electrode.

• JSTS:Journal of Semiconductor Technology and Science
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• 제17권2호
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• pp.216-222
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• 2017

The most prominent challenge for MOSFET scaling is to reduce power consumption; however, the supply voltage ($V_{DD}$) cannot be scaled down because of the carrier injection mechanism. To overcome this limit, a new type of field-effect transistor using positive feedback as a carrier injection mechanism (FBFET) has been proposed. In this study we have investigated the electrical characteristics of a $Si_{1-x}Ge_x$ FBFET with one gate and one-sided $Si_3N_4$ spacer using TCAD simulations. To reduce the drain bias dependency, $Si_{1-x}Ge_x$ was introduced as a low-bandgap material, and the minimum subthreshold swing was obtained as 2.87 mV/dec. This result suggests that a $Si_{1-x}Ge_x$ FBFET is a promising candidate for future low-power devices.