• Journal of the Institute of Electronics Engineers of Korea SP
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• v.39 no.1
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• pp.32-39
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• 2002

Vector quantization for image compression needs expensive encoding time to find the closest codeword to the input vector. This paper proposes a search algorithm for fast vector quantization encoding. Firstly, we derive a robust condition based on the efficient topological structure of the codebook to dramatically eliminate unnecessary matching operations from the search procedure. Then, we Propose a fast search algorithm using the elimination condition. Simulation results show that with little preprocessing and memory cost, the encoding time of the proposed algorithm is reduced significantly while the encoding quality remains the same with respect to the full search algorithm. It is also found that the Proposed algorithm outperforms the existing search algorithms.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.3
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• pp.32-40
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• 2009

In order to reduce time-to-market, the demand for fast fault diagnosis has been increased. In this paper, a fault dropping technique with fault candidate ordering and test pattern ordering for fast fault diagnosis is proposed. Experimental results using the full-scanned ISCAS 89 benchmark circuits show the efficiency of the fault dropping technique with fault candidate ordering and test pattern ordering.

• International Journal of Quality Innovation
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• v.1 no.1
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• pp.89-96
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• 2000

Evolutionary operation (EVOP) is a continuous improvement system which explores a region of process operating conditions by deliberately creating some systematic changes to the process variable levels without jeopardizing the product. It is aimed at securing a satisfactory operating condition in full-scale manufacturing processes, which is generally different from that obtained in laboratory or pilot plant experiments. Information on how to improve the process is generated from a simple experimental design. Traditional EVOP procedures are established on the assumption that the variance of the response variable should be small and stable in the region of the process operation. However, it is often the case that process noises have an influence on the stability of the process. This process instability is due to many factors such as raw materials, ambient temperature, and equipment wear. Therefore, process variables should be optimized continuously not only to meet the target value but also to keep the variance of the response variables as low as possible. We propose a scheme to achieve robust process improvement. As a process performance measure, we adopted the mean square error (MSE) of the replicate response values on a specific operating condition, and used the Kruskal-Wallis test to identify significant differences between the process operating conditions.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.32A no.5
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• pp.60-70
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• 1995

As a Basic study to implement a wide-band photonic switching sysetm, we proposed a scheme of free-space-division-multiplexed photonic switching based on a holographic interconnectio method and carried out simple experiments on it. First, we recorded holgraphic interconnection element array for nonblocking optical interconnections. Just a single stage of the array realizes full optical interconnections between NN${\times}$NN input prots and NN${\times}$NN output ports in 3-D space. Next, in reading of the array for optical internnections, we showed that the zeroth-order diffacted beam could be eliminated in the output port by introducing a right angle prism. The elimination of the zeroth-order diffracted beam reduces optical noise in the output ports and provides conveniences of interconnection control in our scheme. Finally, from the experiments on ON-OFF switching of the optical interconnection paths one by one using a spatial (display of the liquid crystal telecision), we showed the feasibility of photonic wsitching based on the holographic interconnection method. We also estimated approximately the maximum interconnectio scale that can be realized without difficulty with current optical devices.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.28A no.1
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• pp.40-45
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• 1991

It is well known that the conventional differential source-coupled pair uses gates as its input terminals. This input pair provids a high open-loop gain, a large CMRR, and a good PSRR. For these reasons, the input pair has been used widely as an input stages of the differential amplifiers, but a narrow linear input range of this structurelimits its application in the area of some analog circuit design. A novel CMOS source-coupled backgate pair is proposed in this paper. The bulk of MOSFET is exploited and input devices are biased to operate in ohmic region. With this topology, the backgate pair of the wide linear input range and variable transconductance can be obtained. This backgate input differential stage is realized with the size of W/L=50/25 MOSFETs. The results show the nonlinear error is less than $\gamma$1% over 10V full-scale range for the bias current of 200$\mu$A with 10V single power-supply.

• Journal of the Korean Institute of Telematics and Electronics S
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• v.35S no.1
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• pp.130-140
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• 1998

This paper presents a method to estimate subpixel accuracy motion vectors using a mathermatical model withoug interpolation. the proposed method decides the coefficients of mathematical model, which represents the motion vector which is achieved by full search. And then the proposed method estimates subpixel accuracy motion vector from achieved mathematical model. Step by step mathematical models such as type 1, type 2, type 3, modified bype 2, modified type 3, and Partial Interpolation type 3 are presented. In type 1, quadratic polynomial, which has 9 unknown coefficients and models the 3by 3 pixel plane, is used to get the subpixel accuracy motion vectors by inverse matrix solution. In type 2 and 3, each quadratic polynomial which is simplified from type 1 has 5 and 6 unknown coefficients and is used by least square solution. Modified type 2 and modified type 3 are enhanced models by weighting only 5 pixels out of 9. P.I. type 3 is more accurate method by partial interpolation around subpixel which isachieved by type 3. LThese simulation results show that the more delicate model has the better performance and modified models which are simplified have excellent performance with reduced computational complexity.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.32A no.12
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• pp.9-24
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• 1995

In this paper, we proposed and analysed two kinds of priority control mechanism to archive the cell loss rate requirement and the delay requirement of each class. The service classes of our concern are the high time priority class(class 1) and the high loss priority class(class 2). Two kinds of priority control mechanism is divided by the method of storing the arriving class 2 cell in buffer on case of buffer full. The first one is the method which discarding the arriving class 2 cell, the second one is the mothod which storing the arriving class 2 cell on behalf of pushing out the class 1 cell in buffer. In the proposed priority schemes, one cell of the class 1 is transmitted whenever the maximum K cells of the class 2 is transmitted on case of transmitting the class 1 cell and the class 2 cell sequentially. In this paper, we analysed the cell loss rate and the mean cell delay for each class of the proposed priority scheme by using the Markov chain. The analytical results show that the characteristic of the mean cell delay becomes better for the class 1 cell and that of the cell loss rate becomes better for the class 2 cell by selecting properly the cell transfer ratio according to the condition of input traffic.

• Journal of the Korean Institute of Telematics and Electronics B
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• v.33B no.1
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• pp.161-169
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• 1996

This paper presents a new search region prediction method using vector quantization for the motion estimation. We find motion vectors using the full search BMA from two successive frame images first. Then the motion vectors are used for training a codebook. The trained codebook is the predicted search region. We used the unsupervised neural network for VQ encoding and codebook design. A major advantage of formulating VQ as neural networks is that the large number of adaptive training algorithm that are used for neural networks can be applied to VQ. The proposed method reduces the computation and reduce the bits required to represent the motion vectors because of the smaller search points. The computer simulation results show the increased PSNR as compared with the other block matching algorithms.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.38 no.2
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• pp.50-55
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• 2001

In this paper, a 8bit parity checker/generator is designed using a new gate which is proposed to implement the exclusive or(XOR) and exclusive-nor(XNOR) functions for low power consumption on transistor level. Conventional XOR/XNOR gate such as CPL, DPL and CCPL designed to reduce the power consumption has an inverter to get the full swing output signals. But this inverter consumes the major part of power and causes the time delay on CMOS circuits. Thus a new technique was adopted not utilizing inverter in the circuits. The results of simulation by Hspice shows 33% of power reduction compared with CCPL gate when A 8 bit parity checker was made with the proposed new gate using $0.8{\mu}mCMOS$ technology.

• JSTS:Journal of Semiconductor Technology and Science
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• v.4 no.1
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• pp.41-44
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• 2004

The trend of decreasing the minimal structure sizes in microelectronics is still being continued. Therefore in its roadmap the Semiconductor Industries Association predicts a printed minimum MOS-transistor channel length of 10 nm for the year 2018. Although the resolution of optical lithography still dramatically increases, there are known and proved solutions for structure sizes significantly below 50 nm up to now. In this work a new method for the fabrication of extremely small MOS-transistors with a channel length and width below 50 nm with low demands to the used lithography will be explained. It's a further development of our deposition and etchback technique which was used in earlier research to produce transistors with very small channel lengths down to 30 nm, with a scaling of the transistor's width. The used technique is proved in a first charge of MOS-transistors with a channel area of W=200 nm and L=80 nm. The full CMOS compatible technique is easily transferable to almost any other technology line and results in an excellent homogeneity and reproducibility of the generated structure size. The electrical characteristics of such small transistor will be analyzed and the ultimate limits of the technique will be discussed.