• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2003.10a
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• pp.818-823
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• 2003

본 논문에서는 입력 매칭(input matching) BIST(Built-In Self-Test) 회로를 이용한 RF font end의 새로운 결함 검사방법을 제안한다. BIST 회로를 가진 RF front end는 1.8GHz LNA(Low Noise Amplifier: 저 잡음 증폭기)와 이중 대칭 구조의 Gilbert 셀 믹서로 구성되어 있으며, TSMC 0.25$\mu\textrm{m}$ CMOS 기술을 이용하여 설계되었다. catastrophic 결함 및 parametric 변동을 가진 RF front end와 결함을 갖지 않은 RF front end를 판별하기 위해 RF front end의 입력 전압 특성을 조사하였다. 본 방법에서는 DUT(Device Under Test: 검사대상이 되는 소자)와 BIST 회로가 동일한 칩 상에 설계되어 있기 때문에 측정할 때 단지 디지털 전자계와 고주파 전압 발생기만이 필요하며, 측정이 간단하고 비용이 저렴하다는 장점이 있다. BIST 회로가 차지하는 면적은 RF front end가 차지하는 전체면적의 약 10%에 불과하다. 본 논문에서 제안하는 검사기술을 이용하여 시뮬레이션해 본 결과 catastrophic 결함에 대해서는 100%, parametric 변동에 대해서는 약 79%의 결함을 검출할 수 있었다.

• Journal of the Institute of Electronics and Information Engineers
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• v.51 no.12
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• pp.66-71
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• 2014

This paper presents an analog front-end integrated circuit (IC) for medical ultrasound imaging systems using standard $0.18-{\mu}m$ CMOS process. The proposed front-end circuit includes the transmit part which consists of 15-V high-voltage pulser operating at 2.6 MHz, and the receive part which consists of switch and a low-power low-noise preamplifier. Depending on the operation mode, the output driver in the transmit pulser can be reconfigured as the switch in the receive path and thus the area of the overall front-end IC is reduced by over 70% in comparison to previous work. The designed single-channel front-end prototype consumes less than $0.045mm^2$ of core area and can be utilized as a key building block in highly-integrated multi-array ultrasound medical imaging systems.

• Journal of Advanced Navigation Technology
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• v.12 no.6
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• pp.604-610
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• 2008

A 2.4 GHz CMOS RF front-end using for ZigBee application is described The front-end consists of a low noise amplifier and a down-mixer and uses a 2 MHz IF frequency. A common source with resistive feedback and an inductive degeneration are adopted for a low noise amplifier, and a 20 dB gain control step is digitally controlled. A passive mixer for low current consumption is employed. The RF front-end is implemented in 0.18 ${\mu}m$IP6M CMOS process. The measured performance is 4.44 dB NF and -6.5 dBm IIP3 while consuming 3.28 mA current from a 1.8 V supply.

• Journal of Biosystems Engineering
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• v.41 no.3
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• pp.153-160
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• 2016

Purpose: This study was conducted to experimentally investigate the structural safety of and identify critical locations in a front-end loader under impact loads. Methods: Impact and static tests were conducted on a commonly used front-end loader mounted on a tractor. In the impact test, the bucket of the front-end loader with maximum live load was raised to its maximum lift height and was allowed to free fall to a height of 500 mm above the ground where it was stopped abruptly. For the static test, the bucket with maximum live load was raised and held at the maximum lift height, median height, and a height of 500 mm from the ground. Strain gages were attached at twenty-three main locations on the front-end loader, and the maximum stresses and strains were measured during respective impact and static tests. Results: Stresses and strains at the same location on the loader were higher in the impact test than in the static test, for most of measurement locations. This indicated that the front-end loader was put under a severe environment during impact loading. The safety factors for stresses were higher than 1.0 at all locations during impact and static tests. Conclusions: Since the lowest safety factor was higher than 1.0, the front-end loader was considered as structurally safe under impact loads. However, caution must be exercised at the locations having relatively low safety factors because failure may occur at these locations under high impact loads. These important design locations were identified to be the bucket link elements and the connection elements between the tractor frame and front-end loader. A robust design is required for these elements because of their high failure probability caused by excessive impact stress.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.15 no.2
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• pp.273-278
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• 2011

This paper has proposed a dual-band transmitter RF Front-end for IMT-Advanced systems which has been implemented in a 0.13-${\mu}m$ CMOS technology. The proposed dual-band transmitter RF Front-End covers 2300~2700 MHz, 3300~3800 MHz frequency ranges which support 802.11, Mobile WiMAX, and IMT-Advanced system. The proposed dual-band transmitter RF Front-End consumes 45 mA from a 1.2 V supply voltage. The performances of the transmitter RF Front-End are verified through post-layout simulations. The simulation results show a +0 dBm output power at 2 GHz band, and +1.3 dBm output power at 3 GHz band.

• Journal of Ocean Engineering and Technology
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• v.24 no.1
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• pp.166-171
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• 2010

In this paper, the front-end of a digital receiver with a 25 kHz carrier frequency, 5 kHz symbol rate, and any excess-bandwidth is designed using two basic facts. The first is known as the uniform sampling theorem, which states that the sampled sequence might not suffer from aliasing even if its sampling rate is lower than the Nyquist sampling rate if the analog signal is a bandpass one. The other fact is that if the sampling rate is 4 times the center frequency of the sampled sequence, the front-end processing complexity can be dramatically reduced due to the half of the sampled sequence to be multiplied by zero in the demixing process. Furthermore, the designed front-end is simplified by introducing sub-filters and sub-sampling sequences. The designed front-end is composed of an A/D converter, which takes samples of a bandpass filtered signal at a 20 kHz rate; a serial-to-parallel converter, which converts a sampled bandpass sequence to 4 parallel sub-sample sequences; 4 sub-filter blocks, which act as a frequency shifter and lowpass filter for a complex sequence; 4 synchronized switches; and 2 adders. The designed front-end dramatically reduces the computational complexity by more than 50% for frequency shifting and lowpass filtering operations since a conventional front-end requires a frequency shifting and two lowpass filtering operations to get one lowpass complex sample, while the proposed front-end requires only four filtering operation to get four lowpass complex samples, which is equivalent to one filtering operation for one sample.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.8 no.2
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• pp.449-455
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• 2004

This paper presents a novel defect detection method for one chip RF front end with fault detection circuits using input matching measurement. We present a BIST circuit using 40.25{\mu}m$ CMOS technology. We monitor the input transient voltage of the RF front end to differentiate faulty and fault-free RF front end. Catastrophic as well as parametric variation fault models are used to simulate the faulty response of the RF front end. This technique has several advantages with respect to the standard approach based on current test stimulus and frequency domain measurement. Because DUT and fault detection circuits are implemented in the same chip, this test technique only requires use of digital voltmeter (RMS meter) and RF voltage source generator for simpleand inexpensive testing.

• Journal of electromagnetic engineering and science
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• v.8 no.3
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• pp.114-118
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• 2008

Direct-conversion RF front-end for 5-GHz WLAN is implemented in $0.18-{\mu}m$ CMOS technology. The front-end consists of a low noise amplifier, and low flicker noise down-conversion mixers. For the mixer, an inductor is included to resonate out parasitic tail capacitances in the transconductance stage at the operating frequency, thereby improves the flicker noise performance of the mixer, and the overall noise performance of the front-end. The receiver RF front-end has 6.5 dB noise figure, - 13 dBm input IP3, and voltage conversion gain of 20 dB with the power consumption of 30 mW.

• Journal of the Korea Institute of Military Science and Technology
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• v.14 no.5
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• pp.825-832
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• 2011

In this paper, we described the design and measurement results of a Front-End Receiver for S-band active phased array radar. The Front-End Receiver has input P1dB of -4dBm and IIP3 of 7dBm. The measurement results show that gain is $24{\pm}0.7dB$, noise figure are less than 2.3dB over the frequency range of $fc{\pm}0.2GHz$. The Front-End Receiver can protect the receiver path from large input signals with a maximum peak power of multi-kW and recovery time is less than 0.8us. The measurement results satisfy all specifications.

• ETRI Journal
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• v.33 no.6
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• pp.969-972
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• 2011

This letter presents a CMOS RF front-end operating in a subthreshold region for low-power Band-III mobile TV applications. The performance and feasibility of the RF front-end are verified by integrating with a low-IF RF tuner fabricated in a 0.13-${\mu}m$ CMOS technology. The RF front-end achieves the measured noise figure of 4.4 dB and a wide gain control range of 68.7 dB with a maximum gain of 54.7 dB. The power consumption of the RF front-end is 13.8 mW from a 1.2 V supply.