• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2003.10a
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• pp.394-397
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• 2003

Since the speed of operation in the system has been increasing rapidly, chips should have been synchronized. Then, synchronized circuits such as PLL (Phase Locked Loop), DLL (Delay Locked Loop) are used. VCO (Voltage Controled Oscillator) generated a frequency in the PLL has disadvantage such as jitter accumulation. On the other hands, VCDL (Voltage Controled Delay Line) used at DLL has an advantage which has no jitter accumulation. In this paper, a new and improved VCDL structure is suggested.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2004.05a
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• pp.28-31
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• 2004

A Quadrature phase detector for high-speed delay-locked loop is introduced. The proposed Quadrature phase detector is composed of two nor gates and it determines if the phase difference of two input clocks is 90 degrees or not. The delay locked loop circuit including the Quadrature phase detector is fabricated in a 0.18 urn standard CMOS process and it operates at 5 ㎓ frequency. The phase error of the delay-locked loop is maximum 2 degrees and the circuits are robust with voltage, temperature variations.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.15 no.6
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• pp.599-607
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• 2004

In this paper, using phase locked loop(PLL) synthesizer, we introduce a novel but simple and low cost frequency modulation(FM) circuit of a flat peak frequency deviation fur modulation signal whose frequency covers from outside to inside of the loop-bandwidth of PLL. The FM circuit was basically designed to compensate an amount of feedback of the loop filter in PLL. The circuit also includes the capability of the adjustment of peak frequency deviation and of blocking the intereference with the loop filter. The designed circuit was successfully implemented and showed the flat frequency deviation as expected in the design. In addition, the novel measurement method of the wideband FM modulation index is suggested verified With the suggest measurement, it can be successfully shown the designed circuit has the expected frequency deviation.

• ETRI Journal
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• v.30 no.2
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• pp.275-281
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• 2008

A 40 Gb/s clock and data recovery (CDR) module for a fiber-optic receiver with improved phase-locked loop (PLL) circuits has been successfully implemented. The PLL of the CDR module employs an improved D-type flip-flop frequency acquisition circuit, which helps to stabilize the CDR performance, to obtain faster frequency acquisition, and to reduce the time of recovering the lock state in the event of losing the lock state. The measured RMS jitter of the clock signal recovered from 40 Gb/s pseudo-random binary sequence ($2^{31}-1$) data by the improved PLL clock recovery module is 210 fs. The CDR module also integrates a 40 Gb/s D-FF decision circuit, demonstrating that it can produce clean retimed data using the recovered clock.

• Journal of Electrical Engineering and Technology
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• v.2 no.2
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• pp.165-171
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• 2007

This paper proposes a new islanding detection method for inverter-interfaced distributed generators (DG). To detect islanding conditions, this paper calculates the phase angle variation of the system voltage by using the phase-locked loop (PLL) in the inverter controllers. Because almost all inverter systems are equipped with the PLL, the implementation of this method is fairly simple and economical for inverter-interfaced DGs. The detection time can also be shortened by reducing communication delay between the relays and the DGs. The proposed method is based on the fact that islanding conditions result in the frequency and voltage variation of the islanded area. The variation depends on the amount of power mismatch. To improve the accuracy of the detection algorithm, this paper injects small low-frequency reactive power mismatch to the output power of DG.

• Proceedings of the IEEK Conference
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• 2000.11b
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• pp.95-99
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• 2000

New locking algorithm of DLL is proposed to improve the locking speed and low power dissipation in this paper, In spite of using the architecture of delay controller, low power consumption is acquired by operating only one controller at once and fast locking speed is accomplished by initial setting from the coarse controller. The proposed DLL circuit is operated from 50MHz to 200MHz and locked within 6 cycle at all of operating frequency.

• 한국신재생에너지학회:학술대회논문집
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• 2007.11a
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• pp.250-254
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• 2007

As photovoltaic(PV) power generation systems become more common, it will be necessary to investigate islanding detection method for PV systems. Islanding of PV systems can cause a variety of problems and must be prevented. However, if the real and reactive powers of the load and PV system are closely matched, islanding detection by passive methods becomes difficult. Also, most active methods lose effectiveness when there are several PV systems feeding the same island. The active frequency drift positive feedback method(AFDPF) enables islanding detection by forcing the frequency of the voltage in the island to drift up or down. In this paper the research for the minimum value of chopping fraction gain applied digital phase-locked-loop (DPLL) to AFDPF considering output power quality and islanding prevention performance are performed by simulation and experiment according to IEEE Std 929-2000 islanding test.

• Journal of Power Electronics
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• v.16 no.5
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• pp.1939-1949
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• 2016

This paper presents an alternative frequency adaptive grid synchronization technique named HDN-FLL, which can accurately extract the fundamental positive- and negative-sequence components and interested harmonics in adverse three-phase grid voltage. The HDN-FLL is based on the harmonic decoupling network (HDN) consisting of multiple first order complex vector filters (FOCVF) with a frequency-locked loop (FLL), which makes the system frequency adaptive. The stability of the proposed FLL is strictly verified to be global asymptotically stable. In addition, the linearization and parameters tuning of the FLL is also discussed. The structure of the HDN has been widely used as a prefilter in grid synchronization techniques. However, the stability of the general HDN is seldom discussed. In this paper, the transfer function expression of the general HDN is deduced and its stability is verified by the root locus method. To show the advantages of the HDN-FLL, a simulation comparison with other gird synchronization methods is carried out. Experimental results verify the excellent performance of the proposed synchronization method.

• Journal of Power Electronics
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• v.18 no.5
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• pp.1523-1535
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• 2018

High-performance Phase-Locked Loops (PLLs) are critical for grid synchronization in grid-tied power electronic applications. In this paper, a new single-phase All Digital Phase-Locked Loop (ADPLL) is proposed. It features fast transient response and good robustness under distorted grid conditions. It is designed for Field Programmable Gate Array (FPGA) implementation. As a result, a high sampling frequency of 1MHz can be obtained. In addition, a new OSG is adopted to track the power frequency, improve the harmonic rejection and remove the dc offset. Unlike previous methods, it avoids extra feedback loop, which results in an enlarged system bandwidth, enhanced stability and improved dynamic performance. In this case, a new parameter optimization method with consideration of loop delay is employed to achieve a fast dynamic response and guarantee accuracy. The Phase Detector (PD) and Voltage Controlled Oscillator (VCO) are realized by a Coordinate Rotation Digital Computer (CORDIC) algorithm and a Direct Digital Synthesis (DDS) block, respectively. The whole PLL system is finally produced on a FPGA. A theoretical analysis and experiments under various distorted grid conditions, including voltage sag, phase jump, frequency step, harmonics distortion, dc offset and combined disturbances, are also presented to verify the fast dynamic response and good robustness of the ADPLL.

• Proceedings of the KIPE Conference
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• 2017.11a
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• pp.7-8
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• 2017

The Phase-Locked Loop (PLL) is widely used in grid-tie inverter applications to achieve the synchronization between the inverter and the grid. However, its performance is deteriorated when the grid voltage is not pure sinusoidal due to the harmonics and the frequency deviation. Therefore it is important to design a high performance phase-locked loop (PLL) for the single phase inverter applications to guarantee the quality of the inverter output. In this paper a simple method to improve the performance of the PLL for the single phase inverter is proposed. The proposed PLL is able to accurately estimate the fundamental frequency component of the grid voltage even in the presence of harmonic components. In additional its transient response is fast enough to track a change in grid voltage within two cycles of the fundamental frequency. The effectiveness of the proposed PLL is confirmed through the PSIM simulation and experiments.