• Proceedings of the Korean Society of Laser Processing Conference
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• 2006.11a
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• pp.53-81
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• 2006

A COG(Chip on Glass) bonding process that is one of display packaging technology and bonds between driver IC chip and a glass panel using ACF(Anisotropic Conductive Film)has been investigated by using diode laser. This method is possible to raise cure temperature of ACF within one second and can reduce the total process time for COG bonding by a conventional method such as a hot plate. Also we can get good pressure mark on the surface of electrodes and higher bonding strength than that by convention method. Results show that laser COG bonding can give low pressure bonding and decrease a warpage of panel. We believe that it can be applied to fine pitch module.

• Journal of Surface Science and Engineering
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• v.47 no.2
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• pp.63-67
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• 2014

As the demand for fine-pitch FPCB (Flexible Printed Circuit Board) increases, so do the number of applications of sputtered FCCL (Flexible Copper Clad Laminate). Furthermore, as the width between the circuit patterns decreases, greater defects are observed in the migration phenomenon. In this study we observed changes in ion migration in real circuit-pattern width using sputtered FCCL. We found that as the applied voltage and residue thickness of the NiCr seeds increase, ion migration occurs faster. If the NiCr seed layer thickens due to a high cathode power and long deposition time while being sputtered, the NiCr will form a residue that quickly becomes a factor for incurring ion migration.

• Journal of electromagnetic engineering and science
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• v.11 no.1
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• pp.62-69
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• 2011

This paper proposes a novel electrical characterization approach for a high-performance package system using an improved Partial Element Equivalent Circuit (PEEC). As the effect of interconnects becomes a pivotal factor for the performance of high-speed electronic systems, there is a great demand for an accurate equivalent model for interconnects. In particular, an equivalent model of interconnects is established in this paper for the Fine-Pitch Ball Grid Array (FBGA) package using the improved PEEC method. Based on the equivalent model, electrical characteristics are analyzed; furthermore, these are verified through the measurement results of a Vector Network Analyzer (VNA).

• Proceedings of the KIEE Conference
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• 2000.07c
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• pp.2221-2223
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• 2000

본 연구에서는 새로운 개념의 초정밀 가공기술인 LIGA 기술(이하 X-선 가공기술이라 함)을 이용하여 정밀 격벽(barrier ribs) 성형용 Ni 금형을 제작하였다. 먼저 X-ray 투과도가 우수하며 내구성 및 기계적 강도가 뛰어난 새로운 재질의 graphite X-선 마스크를 제작하였으며 한정된 단위면적의 X-선 마스크를 이용하여 X-선 노광 면적을 최대화 할 수 있는 새로운 X-선 exposure 기술을 개발하였다. 제작된 barrier ribs 성형용 초정밀 금형의 전체 size는 170mm X 130mm이며 pitch 간격은 110/55${\mu}m$ $\pm$ 0.7${\mu}m$ 이다.

• Journal of the Semiconductor & Display Technology
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• v.4 no.2 s.11
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• pp.33-37
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• 2005

Bare-chip packaging becomes more popular along with the miniaturization of IT components. In this paper, we have studied flip-chip process, and developed automated bonding system. Among the several bonding method, NCP bonding is chosen and batch-type equipment is manufactured. The dual optics and vision system aligns the chip with the substrate. The bonding head equipped with temperature and force controllers bonds the chip. The system can be easily modified fer other bonding methods such as ACF.

• The Proceeding of the Korean Institute of Electromagnetic Engineering and Science
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• v.24 no.2
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• pp.23-34
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• 2013

Over the past several decades in the microelectronics industry, devices have gotten smaller, thinner, and lighter, without any accompanying degradation in quality, performance, and reliability. One permanent and deniable trend in packaging as well as wafer fabrication industry is system integration. The proliferating options for system integration, recently, are driving change across the overall semiconductor industry, requiring more investment in developing, ramping and supporting new die-, wafer- and board-level solution. The trend toward 3D system integration and miniaturization in a small form factor has accelerated even more with the introduction of smartphones and tablets. In this paper, the key issues and state of the art for system integration in the packaging process are introduced, especially, focusing on ease transition to next generation packaging technologies like through silicon via (TSV), 3D wafer-level fan-out (WLFO), and chip-on-chip interconnection. In addition, effective solutions like fine pitch copper pillar and MEMS packaing of both advanced and legacy products are described with several examples.

• Journal of the Korean Society for Precision Engineering
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• v.16 no.3 s.96
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• pp.25-29
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• 1999

The lead frame manufactured by press stamping process, is an important part of semiconductor. The recent technical trend of semiconductor, chip sized and high performance package technology, requires the lead frame to be of more multi-leads and of fine ILP (Inner Lead Pitch). As the ILP is getting finer, its corresponding punch of the stamping die is getting narrower. The punch narrower than its stamping limit has been broken due to local buckling. This paper analyzed the phenomena of punch breakdown. Moreover, the punch design was modified to increase the critical limit of buckling force. This paper, also, suggested new design rules of the punch, which asks the modification of its lead frame design that has to be considered in the stage of semiconductor package design. The new design rules of lead frame design yields a good reliability of semiconductor package as well as a good quality of lead frame.

• Proceedings of the Korean Institute of Surface Engineering Conference
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• 2012.05a
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• pp.134-134
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• 2012

패키징용 PCB를 비롯한 대부분의 PCB는 동박을 소재로 사용하게 된다. 패키징용 PCB를 중심으로 한 PCB의 협피치화에 대응하기 위해서 전해동박의 저조도화, 박형화에 대한 필요성이 증대되고 있다. 동박의 제조공정은 드럼상에 Cu를 도금하는 공정(EM 공정), 표면에 조도를 부여하고 내열, 방청성 등을 부여하는 공정(TM공정), 절단하는 공정(SM공정)으로 이루어진다. 동박의 저조도화를 위해서는 EM 및 TM공정의 첨가제 개발 및 저조도 도금 공정 개발이 필요하다. 박형화를 위해서는 얇은 두께에서도 핸들링이 가능하도록 동박의 강도를 높이거나 제조공정을 개선하는 연구가 필요하다. 본 발표에서는 이러한 전해동박의 제조공정을 소개하고 협피치화 대응을 비롯한 전해동박의 개발 방향에 대해서 소개하고자 한다.

• Proceedings of the Korean Society of Propulsion Engineers Conference
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• 2008.11a
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• pp.72-77
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• 2008

The function of the Reaction Control System include roll, pitch and yaw control of the launch vehicles and fine control maneuvers and precision upper stage orientation before separation of one or more payload. This paper describes the overview of commercial launchers, current technology trend for RCS of launch vehicles, and development status of medium class thruster for RCS.

• Journal of the Semiconductor & Display Technology
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• v.22 no.4
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• pp.38-47
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• 2023

Three dimensional (3D) packaging is a next-generation packaging technology that vertically stacks chips such as memory devices. The necessity of 3D packaging is driven by the increasing demand for smaller, high-performance electronic devices (HPC, AI, HBM). Also, it facilitates innovative applications across another fields. With growing demand for high-performance devices, companies of semiconductor fields are trying advanced packaging techniques, including 2.5D and 3D packaging, MR-MUF, and hybrid bonding. These techniques are essential for achieving higher chip integration, but challenges in mass production and fine-pitch bump connectivity persist. Advanced bonding technologies are important for advancing the semiconductor industry. In this review, it was described 3D packaging technologies for chip integration including mass reflow, thermal compression bonding, laser assisted bonding, hybrid bonding.