• Journal of Sensor Science and Technology
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• v.22 no.3
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• pp.207-211
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• 2013

In this research, the pH sensor was developed using CNT nanosheet with Nafion coating for the advanced medical sensor such as a blood gas analyzer. The CNT nanosheet was formed by dielectrophoresis and water-meniscus between cantilever-type electrodes. Then, the process of the heat annealing and the Nafion coating was conducted for reducing contact resistance and giving proton selectivity respectively. We measured the response of the pH sensor as the electrolyte-gated CNT-nanosheet field effect transistor. The sensor showed a linear current ratio in a similar range of the normal blood pH. A calibration method for decreasing of the response variation among sensors has also been introduced. Coefficient of variance of the pH sensor was decreased by applying the calibration method. A linear relation between the calibrated response of the sensors and pH variance was also obtained. Finally, the pH sensor with a high resolution was fabricated and we verify the feasibility of the sensor by applying the calibration method.

• Journal of Microbiology and Biotechnology
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• v.10 no.6
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• pp.873-876
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• 2000

Short tendem repeat (STR) loci have been used in the field of forensic science. There are literally hundreds of STR systems which have been mapped throughout the human genome. These STR loci are found in almost every chromosome in the genome. They may be amplified using a variety of PCR primers. In this study, a DNA genotyping system based on the multiplex amplification of highly polymorphic STR loci was developed. Three STR loci with nonoverlapping allele size ranges have been utilized in the multiplex amplification including the Neurotensin receptor gene, D21S11, and Human tyrosine hydroxylase gene. The optimal condition for triplex PCr was obtained in a solution with a total volume of $25{\mu}l$ containing 2.0 U of Taq polymerase, 3 mM of $MgCl_2$, $300{\mu}M$ of dNTP, 10 pmole of each primer set, an annealing temperature of $62^{\circ}C$, and 35 cycles. The optimized condition was successfully employed in a family paternity test.

• Korean Journal of Materials Research
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• v.15 no.5
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• pp.301-305
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• 2005

We fabricated nickel silicide layers on whole non-patterned wafers from $p-Si(100)SiO_2(200nm)$/poly-Si(70 nm)mn(40 nm) structure by 40 sec rapid thermal annealing of $500\~900^{\circ}C$. The sheet resistance, cross-sectional microstructure, surface roughness, and phase analysis were investigated by a four point probe, a field emission scanning electron microscope, a scanning probe microscope, and an X-ray diffractometer, respectively. Sheet resistance was as small as $7\Omega/sq$. even at the elevated temperature of $900^{\circ}C$. The silicide thickness and surface roughness increased as silicidation temperature increased. We confirmed the nickel silicides iron thin nickel/poly-silicon structures would be a mixture of NiSi and $NiSi_2$ even at the $NiSi_2$ stable temperature region.

• Proceedings of the Materials Research Society of Korea Conference
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• 2003.11a
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• pp.120-120
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• 2003

The metallic oxide nanomaterials including ZnO, Ga$_2$O$_3$, TiO$_2$, and SnO$_2$ have been synthesized by a number of methods including laser ablation, arc discharge, thermal annealing procedure, catalytic growth processes, and vapor transport. We have been interested in preparing the nanomaterials of Ga$_2$O$_3$, which is a wide band gap semiconductor (E$_{g}$ =4.9 eV) and used as insulating oxide layer for all gallium-based semiconductor. Ga$_2$O$_3$ is stable at high temperature and a transparent oxide, which has potential application in optoelectronic devices. The Ga$_2$O$_3$ nanoparticles and nanobelts were produced using GaN single crystals, which were grown by flux method inside SUS$^{TM}$ cell using a Na flux and exhibit plate-like morphologies with 4 ~ 5 mm in size. In these experiments, the conventional electric furnace was used. GaN single crystals were pulverized in form of powder for the growth of Ga$_2$O$_3$ nanomaterials. The structure, morphology and composition of the products were studied mainly by X-ray diffraction (XRD), field emission scanning electron microscopy (FESEM), and high-resolution transmission electron microscopy (HRTEM).).

• Transactions on Electrical and Electronic Materials
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• v.17 no.5
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• pp.302-305
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• 2016

In this paper, a low on-resistance and high current driving capability trench gate power metal-oxide-semiconductor field-effect transistor (MOSFET) incorporating a current sensing feature is proposed and evaluated. In order to realize higher cell density, higher current driving capability, cost-effective production, and higher reliability, self-aligned trench etching and hydrogen annealing techniques are developed. While maintaining low threshold voltage and simultaneously improving gate oxide integrity, the double-layer gate oxide technology was adapted. The trench gate power MOSFET was designed with a 0.6 μm trench width and 3.0 μm cell pitch. The evaluated on-resistance and breakdown voltage of the device were less than 24 mΩ and 105 V, respectively. The measured sensing ratio was approximately 70:1. Sensing ratio variations depending on the gate applied voltage of 4 V ~ 10 V were less than 5.6%.

• Proceedings of the KIEE Conference
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• 1988.11a
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• pp.147-150
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• 1988

Since the integration level of VLSI circuits progresses very quickly, a highly reliable thin $SiO_2$ film is required to fabricate a small-geometry MOS device. In the present study we have attempted to eliminate the failure-causing defects that develop in thin oxide films during the oxidation step by performing a long-time preoxidation and postoxidation annealing. The TDDB test and the copper decoration method were used to calculate the oxide defects density of MOS device. The dielectric reliability of high-quality thin oxides have been studied by using the time-zero-dielectric-breakdown (ramp-voltage-stressed I-V) and time-dependent-dielectric -breakdown (Constant-stressed I-V) tests. Failure times against temperature and electric field are examined and acceleration factors are abtained for each parameter. Based on the data obtained, breakdown wearout limitation for thin oxide films is estimated.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2001.07a
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• pp.70-73
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• 2001

MFIS(Metal-ferroelectric-insulator- semiconductor) structures using silicon oxynitride(SiON) buffer layers were fabricatied and demonstrated nonvolatile memory operations. Oxynitride(SiON) films have been formed on p-Si(100) by RTP(rapid thermal process) in O$_2$+N$_2$ ambient at 1100$^{\circ}C$. The gate leakage current density of Al/SiON/Si(100) capacitor was about the order of 10$\^$-8/ A/cm$^2$ at the range of ${\pm}$ 2.5 MV/cm. The C-V characteristics of Al/LiNbO$_3$/SiON/Si(100) capacitor showed a hysteresis loop due to the ferroelectric nature of the LiNbO$_3$ thin films. Typical dielectric constant value of LiNbO$_3$ film of MFIS device was about 24. The memory window width was about 1.2V at the electric field of ${\pm}$300 kV/cm ranges.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 1993.11a
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• pp.137-140
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• 1993

Electrical properties and thermal annealing effects of $C_{22}$-quinolium(TCNQ) Langmuir-Blodgett(LB) films were studied. Typical current-voltage(I-V) characteristics along the perpendicular direction chow an anomalous behavior of breakdown near the electric-field strength of $10^{6}$V/cm. To see the thermal influence of the specimen, current was measured as a function of temperature(20∼$180^{\circ}C$). It shows that the current increases about 4 orders of magnitude near 60∼$70^{\circ}C$ and remains constant far a while up to ∼$150^{\circ}C$ and then suddenly drops. Such increase of current near 60∼$70^{\circ}C$ seems tn be related to a softness of alkyl chains. Besides the electrical measurements, UV/visible absorption(300∼800 nm) of the thermally annealed sample was measured to see the internal-structure change. It is found that there are four characteristic peaks. At 494 nm, the optical absorption of the thermally annealed specimen at $60^{\circ}C$ starts increase and stays almost constant upto∼ $140^{\circ}C$. And eventually it disappears above $180^{\circ}C$. After heat treatment of the specimen up to $150^{\circ}C$, Uv/visible absorption was measured while cooling.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2002.07b
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• pp.570-573
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• 2002

Pb(Zr0.52Ti0.48)O3 (PZT) thin films were deposited on the Pt/Ti bottom electrode by rf magnetron sputtering method from target containing 5%, 25% and 50% Pb excess for applying ferroelectric random access memory (FRAM). PZT films were deposited at $300^{\circ}C$ and then they were crystallized by rapid thermal annealing (RTA) at $700^{\circ}C$. After RTA treatment, our results showed that all PZT films indicated perovskite polycrystalline structure with preferred orientation (110) and no pyrochlore phase was observed by X-ray diffraction (XRD) and by Scanning electron microscopy (SEM). A well-fabricated PZT film of excess Pb 25% capacitor showed a leakage current density in the order of $2.63{\times}10^{-7}A/cm^2$ at 100kV/cm, a remanent polarization of $3.385{\mu}C/cm^2$ and a coercive field of 41.32 kV/cm. The results showed that Pb excess of target affects to electrical properties of PZT thin film.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2006.11a
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• pp.133-134
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• 2006

A simple doping method to fabricate a very thin channel body of the n-type fin field-effect-transistor (FinFET) with a 20 nm gate length by solid-phase-diffusion (SPD) process is presented. Using As-doped spin-on-glass as a diffusion source of arsenic and the rapid thermal annealing, the n-type source-drain extensions with a three-dimensional structure of the FinFET devices were doped. The junction properties of arsenic doped regions were investigated by using the $n^+$-p junction diodes which showed excellent electrical characteristics. Single channel and multi-channel n-type FinFET devices with a gate length of 20-100 nm was fabricated by As-SPD and revealed superior device scalability.