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High-Current Trench Gate DMOSFET Incorporating Current Sensing FET for Motor Driver Applications

  • Kim, Sang-Gi (Electronics and Telecommunications Research Institute) ;
  • Won, Jong-Il (Electronics and Telecommunications Research Institute) ;
  • Koo, Jin-Gun (Electronics and Telecommunications Research Institute) ;
  • Yang, Yil-Suk (Electronics and Telecommunications Research Institute) ;
  • Park, Jong-Moon (Electronics and Telecommunications Research Institute) ;
  • Park, Hoon-Soo (Department of Green Energy Engineering, Uiduk University) ;
  • Chai, Sang-Hoon (Department of Electronic Engineering, Hoseo University)
  • Received : 2016.04.27
  • Accepted : 2016.08.31
  • Published : 2016.10.25

Abstract

In this paper, a low on-resistance and high current driving capability trench gate power metal-oxide-semiconductor field-effect transistor (MOSFET) incorporating a current sensing feature is proposed and evaluated. In order to realize higher cell density, higher current driving capability, cost-effective production, and higher reliability, self-aligned trench etching and hydrogen annealing techniques are developed. While maintaining low threshold voltage and simultaneously improving gate oxide integrity, the double-layer gate oxide technology was adapted. The trench gate power MOSFET was designed with a 0.6 μm trench width and 3.0 μm cell pitch. The evaluated on-resistance and breakdown voltage of the device were less than 24 mΩ and 105 V, respectively. The measured sensing ratio was approximately 70:1. Sensing ratio variations depending on the gate applied voltage of 4 V ~ 10 V were less than 5.6%.

Keywords

1. INTRODUCTION

Current sensing power metal-oxide-semiconductor field-effect transistors (MOSFETs) provide a highly effective method of measuring load current in power electronic circuits. Current sensing is an essential function and necessary for precision closed-loop control applications such as motor control, communications infrastructure, and power management circuits. Accurate current monitoring provides designers with critical instantaneous information, such as motor torque, the efficiency of a dc-to-dc converter, the biased current of a power transistor, or diagnostic information [1]. The current sensing power MOSFET incorporating a current sensing feature provides a simple circuit solution for over current protection without any additional sensing elements and offers a low loss method of measuring the load current, eliminating the need for a shunt resistor [2,3]. The current sensing operation is based on the principle of matched devices in integrated circuits. The current sensing power MOSFET essentially comprises two matched power MOSFETs: the main switching power MOSFET and a much smaller sensing MOSFET. These devices are implemented with relatively the same device structure, although they have separated source pins. The ratio of switching cells to sense cells is very large, and when the current flows through the main MOSFET, a much smaller current is produced through the sensing MOSFET. Therefore, the use of an internal sensing field-effect transistor (FET) to monitor the current through the load switch provides an effective way to implement lossless and low cost monitoring and to protect circuits.

In this paper, we propose and evaluate a high-density and high-current trench gate power MOSFET (100 V / 200 A) with a current sensing feature, while adopting the double layer gate technology. Cost-effective self-aligned trench etching using a side-wall spacer and hydrogen annealing techniques is developed to increase cell density and reliability. Moreover, the double layer stacked gate oxide technology was adapted to improve the gate oxide reliability. The trench gate power MOSFET was designed with a 0.6 μm trench width and a 3.0 μm cell pitch. The on-chip current sensing FET has the same structure and geometry as that of the main switching power MOSFET, but has separated source pins. The evaluated on-resistance and breakdown voltage of the fabricated device were less than 24 mΩ and 105 V, respectively. The measured sensing ratio was approximately 70:1. The sensing ratio variation depending on the gate applied voltage of 5 V ~ 10 V was revealed to be less than 5.6%.

 

2. EXPERIMENTS

In order to fabricate high-current trench gate MOSFETs, a starting n-type substrate with 10 μm-thick n-epi layer was used. Firstly, boron ion (~2.5×1013/cm2) implantation and drive-in were performed to form a p-body region. Manufacturing a high aspect ratio trench structure, an oxide spacer which acts as an etching mask is formed by deposition and reactive ion etching (RIE) of tetra-ethyl-ortho-silicate (TEOS) film. The resulting width and depth of the trench was 0.6 μm and 1.65 μm, respectively. Following trench etching, post trench etching treatment processes of SC1 cleaning and sacrificial oxidation were performed. The purposes of these treatments are to improve the thickness uniformity of the top convex and the bottom concave corners in the trench edges, to reduce the roughness of the trench sidewall, and to eliminate the damaged layer of the trench surface [4]. Moreover, in order to improve the gate oxide integrity, the gate oxide was grown by double-layer technology [5-7]. After removing the sacrificial oxide film, the first gate oxide layer was grown on the trench by thermal oxidation. Because relatively thin single thermal oxide is not sufficient to overcome the local oxide thinning at trench corners, which degrades gate oxide reliability, 200 Å- thick upper oxide film was deposited by a high-temperature oxide (HTO) process. The resulting thickness of the double-layer gate oxide was evaluated to be about 400 Å. This process was followed by deposition and doping of polysilicon to fill the trenches, and arsenic and boron ions were then implanted for n+ source and p+ body contacts. The cross-sectional SEM photographs of the current sensing power MOSFET are shown in Fig. 1. To simplify the processing steps and to minimize the mask steps, the sensing FET is processed at the same condition as the switching Double-diffused MOSFET (DMOSFET).

Fig. 1.SEM photographs of current sensing trench gate MOSFET; (a) top view of trench cells after trench etching, (b) cross-sectional image of fabricated trench gate MOSFET.

Figure 2 presents the top view of the current sensing trench gate MOFET which has a continuous current rating of 200 A; the breakdown voltage of 100 V is presented. The optimally designed trench gate MOSFET, eliminating junction gate field-effect transistor (JFET) resistance, provides high-density as well as low on-resistance properties. Sensing and main switching MOSFET cells are designed with the same geometry and schematic topology. As shown in Fig. 2, the majority of the die area is covered with the source metal of the switching DMOSFET, while the small area of the sensing FET is located at the side. The proper location of sensing is often considered to be the center of the main cell for the best matching of process and temperature variations. However, in order to accommodate multiple wire bonds of switching MOSFETs, the sensing FET was placed at the side of the chip. A vertical diffused trench gate MOSFET consists of a large number of parallel cells that share the current of the linear operating regime of a MOSFET. Few cells can be used to provide a sensing signal proportional to the main switching current. The current sensing DMOSFET consisting of a sensing FET in parallel with a switching MOSFET has four terminals.

Fig. 2.Full layout and detailed cell topology of 200 A / 100 V rating current sensing trench gate MOFETs.

The pin configuration is shown in Fig. 3. Essentially, the current sensing and switching DMOSFETs, residing on the same p-substrate, are implemented with the same device structure and cell geometry, while sharing common drain and gate electrodes but having separated source terminals. The separate source connection provides the sense signal to the motor control (ICs) and is called a mirror terminal.

Fig. 3.Equivalent circuit and schematic terminal diagram of current sensing DMOSFET.

The relative active area dimension of these two devices determines the amount of current that is split between the source and mirror terminals.

 

3. RESULTS AND DISCUSSION

Figure 4(a) illustrates the typical drain current (ID) versus drain-to-source voltage (VDS) characteristics of the trench gate DMOSFET at various gate voltages (VGS). The device is designed with a 0.6 μm trench width and a 3.0 μm cell pitch. It is found that with a gate voltage higher than 5 V, the device operates at a linear region up to 200 A. Moreover, the device shows fairly safe operation up to the drain current of more than 200 A at the gate voltage of 8 V and the corresponding drain voltage of 10 V. The measured on-resistance of the switching DMOSFET is 24 mΩ under the applied gate voltage and drain current of 10 V and 80 A, respectively. In Fig. 4(b), the threshold voltage of the device with the double-layer gate oxide 400 Å was approximately 1.6 V. The threshold voltage is defined as the gate voltage when the drain current reaches 250 μA, while the drain voltage is fixed at 0.1 V. To maintain a low threshold voltage and simultaneously improve gate oxide reliability, a double-layer gate oxide (thermal oxide 200 Å / HTO 200 Å) technology was adapted.

Fig. 4.(a) Typical drain current (ID) versus drain-to source voltage (VDS) characteristics and (b) threshold voltage characteristics depending on the drain voltages of the trench gate DMOSFET.

Figure 5 shows the breakdown voltage characteristics of the n-channel switching FET. The measured breakdown, which is measured at the drain current of 250 μA with increasing drain voltage while the gate voltage is fixed at 0 V, is revealed to be approximately 105 V. Considering the lower leakage current level, the off-state characteristic of this DMOSFET shows fairly good performance.

Fig. 5.Measured breakdown voltage characteristics of the trench gate DMOSFET.

The ratio of source current to mirror current is specified by the current mirror ratio (n). This ratio is defined for conditions where both the source and mirror terminals are held at the same potential. Since the load current is approximately equal to the source current, the current mirror ratio also describes the ratio of load current to the sense current. On the other hand, the sensing ratio is also defined as the ratio of the on-resistance of the sensing FET, and that of the switching MOSFET is defined as the ratio of the active areas of switching FET and sensing FET [3]. Generally, an on-resistance of a sensing FET is much higher than that of a switching MOSFET.

In Fig. 6, the measured current sensing ratio of the trench gate DMOSFET (100 V / 200 A) as a function of drain applied voltages at a constant gate voltage of 5 V is presented. As shown in Fig. 6, the current sensing ratio is observed to be 70 at room temperature, and its variation depending on the drain applied voltages was less than 5.9%. According to the previous research [8], at the linear operating region, the sensing ratio variation is subject to gate applied voltages.

Fig. 6.Tested sensing ratio of trench gate DMOSFET as a function of drain voltage under the constant gate voltage of 5 V.

Figure 7 illustrates the sensing ratio variations depending on the gate applied voltages for the constant drain current of 100 A under the room temperature condition. As shown in Fig. 7, the change of sensing ratio over gate voltage of 4 V to 10 V is slightly increased with decreasing gate voltage and measures less than 5.6%. From these test results of sensing ratio variations, the power MOSFET of this work can provide a precise signal to control ICs over the wide ranges of different operating gate voltages and drain currents.

Fig. 7.Sensing ratio variations depending on the gate voltages measured at constant drain current of 100 A condition.

 

4. CONCLUSIONS

This paper describes the proposed and evaluated high-density, low on-resistance and high current driving capability trench gate power MOSFET incorporating a current sensing feature. Utilizing the self-aligned trench etching using the sidewall spacer and hydrogen annealing techniques, we improve the cell density and reliability of the device. Moreover, in order to prevent the gate oxide degradation caused by local gate oxide thinning at the trench corners, the gate oxide was grown using double layers. The resulting thickness of the double-layer gate oxide is 400 Å. An on-chip current sensing FET was designed to have the same structure and geometry as those of the trench gate switching MOSFET. The trench gate MOSFET designed with a 0.6 μm trench width and a 3.0 μm cell pitch demonstrates a fairly safe operation at the drain current of more than 200 A. It was observed that the current sensing ratio measures 70 at room temperature. The sensing ratio variations as functions of drain and gate voltages are shown to be less than 5.9% and 5.6%, respectively. Considering the advantages of low power loss and low cost, the trench gate MOSFET of this work can be successfully used for power system applications where current control or over current protection is required.

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