• Journal of the Korea Society of Computer and Information
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• v.24 no.4
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• pp.107-112
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• 2019

Failure testing is a test that verifies that the system is operating in accordance with failure response requirements. A typical failure test approaches the operating system by identifying and testing system problems caused by unexpected errors during the operational phase. In this paper, we study how to evaluate these Failure at the software development stage. Evaluate the probability of failure due to code changes through the complexity and duplication of the code, and evaluate the probability of failure due to exceptional situations with bugs and test coverage extracted from static analysis. This paper studies the possibility of failure based on the code quality of software development stage.

• International Journal of Quality Innovation
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• v.8 no.1
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• pp.137-153
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• 2007

Failure mode and effects analysis (FMEA) is a preventive technique in reliability management field. The successful implementation of FMEA technique can avoid or reduce the probability of system failure and achieve good product quality. The FMEA technique had applied in vest scopes which include aerospace, automatic, electronic, mechanic and service industry. The marking process is one of the back ends testing process that is the final process in semiconductor process. The marking process failure can cause bad final product quality and return although is not a primary process. So, how to improve the quality of marking process is one of important production job for semiconductor testing factory. This research firstly implements FMEA technique in laser marking process improvement on semiconductor testing factory and finds out which subsystem has priority failure risk. Secondly, a CCD position solution for priority failure risk subsystem is provided and evaluated. According analysis result, FMEA and CCD position implementation solution for laser marking process improvement can increase yield rate and reduce production cost. Implementation method of this research can provide semiconductor testing factory for reference in laser marking process improvement.

• Journal of Korean Society for Quality Management
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• v.17 no.2
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• pp.17-26
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• 1989

This paper is concerned with forecasting the existing number of errors in the computer software and optimizing the stopping time of the software test based upon the forecasted number of errors. The most commonly used models have assessed software reliability under the assumption that the software failure late is proportional to the current fault content of the software but invariant to time since software faults are independents of others and equally likely to cause a failure during testing. In practice, it has been observed that in many situations, the failure rate decrease. Hence, this paper proposes a mathematical model to describe testing situations where the failure rate of software limearly decreases proportional to testing time. The least square method is used to estimate parameters of the mathematical model. A cost model to optimize the software testing time is also proposed. In this cost mode two cost factors are considered. The first cost is to test execution cost directly proportional to test time and the second cost is the failure cost incurred after delivery of the software to user. The failure cost is assumed to be proportional to the number of errors remained in the software at the test stopping time. The optimal stopping time is determined to minimize the total cost, which is the sum of test execution cast and the failure cost. A numerical example is solved to illustrate the proposed procedure.

• Journal of Applied Reliability
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• v.5 no.2
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• pp.221-239
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• 2005

General chip SMD parts(chip resistance, chip capacitor, chip varistor etc.) are very wide used electronics parts for IT units. But, failure modes are indistinct for these chip parts. In factory and field the failure modes are recognized to accidental failure mode caused by potential defect. In this paper used chip varistor ALT(Accelerate Life Test) test for verify general failure modes in chip SMD parts. Also the results are useful for general chip SMD ALT tests.

• Journal of the Korean Society for Nondestructive Testing
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• v.27 no.6
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• pp.520-530
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• 2007

Combination of the parametric and the wavelet analyses of acoustic emission (AE) signals was applied to identify the failure modes in carbon fiber reinforced plastic (CFRP) composite laminates during tensile testing. AE signals detected by surface mounted lead-zirconate-titanate (PZT) and polyvinylidene fluoride (PVDF) sensors were analyzed by parametric analysis based on the time of occurrence which classifies AE signals corresponding to failure modes. The frequency band level-energy analysis can distinguish the dominant frequency band for each failure mode. It was observed that the same type of failure mechanism produced signals with different characteristics depending on the stacking sequences and the type of sensors. This indicates that the proposed method can identify the failure modes of the signals if the stacking sequences and the sensors used are known.

• Proceedings of the Korean Reliability Society Conference
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• 2005.06a
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• pp.51-67
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• 2005

General chip SMD parts(chip resistance, chip capacitor, chip varistor etc.) are very wide sed electronics parts for IT units. But, failure modes are indistinct for these chip parts. In factory and field the failure modes are recognized to accidental failure mope caused by potential defect. In this paper used chip varistor ALT(Accelerate Life Test) test for verify general failure modes in chip SMD parts. Also the results are useful for general chip SMD ALT tests.

• Journal of Korean Society for Quality Management
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• v.29 no.4
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• pp.92-102
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• 2001

Software testing during development and operation should exercise to obtain the desired software quality and leave failure data set. So far, many software reliability models are classified and can be used to measure a software reliability only based on its failure history But, in practice, developers or testers of software systems must decide which existing software reliability model can be fitted. In this paper, we will show that an appropriate reliability model can be selected by considering relations between characteristics of each testing environment and models' assumptions. Several methods of software testing are presented and discussed. Also, unit test, integrated test, function test and system test that are sequentially exercised during development will be introduced.

• Journal of Korean Institute of Industrial Engineers
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• v.29 no.2
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• pp.145-149
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• 2003

We consider the estimation of failure rate and acceleration factor under type-I censoring without using acceleration model when testing is conducted in only one highly accelerated condition. Failure times of an item are assumed to be exponentially distributed. It is also assumed that the uncertainty about the acceleration factor, the failure time contraction ratio between accelerated condition and use condition, can be modeled by the uniform or gamma prior distribution of appropriate parameters. We respectively use Bayes and maximum likelihood approaches to estimate acceleration factor and failure rate in the use condition. An example is given to show how the method can be applied.

• Journal of the Korean Statistical Society
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• v.11 no.2
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• pp.77-87
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• 1982

The choice if constants that define a life testing procedure is considered in terms of the test termination time (censoring time) and the number of items to be tested subject to a given range of variance of the expected life time, where the failure time of life testing is exponentially distributed.

• Journal of Applied Reliability
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• v.7 no.4
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• pp.137-148
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• 2007

Rapid increase of embedded systems in electronic and mechanical control systems requires reliable and error-free embedded software. State-based testing methods like FSM are usually used to assure the reliability of embedded software. However, because of possibility of explosion of test cases, only partial test cases are considered in practical tests, which cannot guarantee that all the possible errors are investigated. This study proposes a test procedure based on failure mechanisms that may occur in embedded systems, which can not only assure that certain kinds of possible errors are detected but reduce the testing time. The proposed procedure is applied to vehicle air control system.