• Journal of IKEEE
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• v.9 no.2 s.17
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• pp.152-160
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• 2005

A prescaler is an essential building block for PLL-based frequency synthesizers and must satisfy high-speed and low-power characteristics. The design of D-flip flips used in the prescaler implementation is thus critical. Conventional TSPC D-flip flops suffer from glitches, unbalanced propagation delay, and unnecessary charge/discharge at internal nodes in precharge phase, which results in increased power consumption. In this paper a new dynamic D-flip flop is proposed to overcome these problems. Glitches are minimized using discharge suppression scheme, speed is improved by making balanced propagation delay, and low power consumption is achieved by removing unnecessary discharge. The proposed D-flip flop is employed in designing a 128/129 dual-modulus prescaler using $0.18{\mu}m$ CMOS process parameters. The designed prescaler operates up to 5GHz while conventional one can operate up to 4.5GHz under same conditions. It consumes 0.394mW at 4GHz that is a 34% improved result compared with conventional one.

• International Journal of Computer Science & Network Security
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• v.21 no.11
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• pp.345-353
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• 2021

Cloud computing represent a new era of computing that's forms through the combination of service-oriented architecture (SOA), Internet and grid computing with virtualization technology. Virtualization is a concept through which every cloud is enable to provide on-demand services to the users. Most IT service provider adopt cloud based services for their users to meet the high demand of computation, as it is most flexible, reliable and scalable technology. Energy based performance tradeoff become the main challenge in cloud computing, as its acceptance and popularity increases day by day. Cloud data centers required a huge amount of power supply to the virtualization of servers for maintain on- demand high computing. High power demand increase the energy cost of service providers as well as it also harm the environment through the emission of CO₂. An optimization of cloud computing based on energy-performance tradeoff is required to obtain the balance between energy saving and QoS (quality of services) policies of cloud. A study about power usage of resources in cloud data centers based on workload assign to them, says that an idle server consume near about 50% of its peak utilization power [1]. Therefore, more number of underutilized servers in any cloud data center is responsible to reduce the energy performance tradeoff. To handle this issue, a lots of research proposed as energy efficient algorithms for minimize the consumption of energy and also maintain the SLA (service level agreement) at a satisfactory level. VM (virtual machine) consolidation is one such technique that ensured about the balance of energy based SLA. In the scope of this paper, we explore reinforcement with fuzzy logic (RFL) for VM consolidation to achieve energy based SLA. In this proposed RFL based active VM consolidation, the primary objective is to manage physical server (PS) nodes in order to avoid over-utilized and under-utilized, and to optimize the placement of VMs. A dynamic threshold (based on RFL) is proposed for over-utilized PS detection. For over-utilized PS, a VM selection policy based on fuzzy logic is proposed, which selects VM for migration to maintain the balance of SLA. Additionally, it incorporate VM placement policy through categorization of non-overutilized servers as- balanced, under-utilized and critical. CloudSim toolkit is used to simulate the proposed work on real-world work load traces of CoMon Project define by PlanetLab. Simulation results shows that the proposed policies is most energy efficient compared to others in terms of reduction in both electricity usage and SLA violation.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.31 no.3A
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• pp.360-367
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• 2006

In this paper, we designed a digital codec of an RFID tag for EPC global generation 2 class 1. There are a large number of studies on RRD standard and anti-collision algorithm but few studies on the design of digital parts of the RFID tag itself. For this reason, we studied and designed the digital codec hardware for EPC global generation 2 class 1 tag. The purpose of this paper is not to improve former studies but to present the hardware architecture, an estimation of hardware size and power consumption of digital part of the RFID tag. Results are synthesized using Synopsys with a 0.35um standard cell library. The hardware size is estimated to be 111640 equivalent inverters and dynamic power is estimated to be 10.4uW. It can be improved through full-custom design, but we designed using a standard cell library because it is faster and more efficient in the verification and the estimation of the design.

• International journal of advanced smart convergence
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• v.11 no.3
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• pp.222-228
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• 2022

As a means to cope with the climate change crisis caused by global warming, automobile manufacturers continue to make efforts to use the driving energy of vehicles as electricity. As a result, parts industry such as battery, motor, and controller are attracting attention. China is often seen in large cities, with electric vehicles such as electric bicycles, electric motorcycles, and small electric vehicles popularized and commercialized, mainly in large cities. However, small electric vehicles are not popular in Korea, which is why the country's topography is high in hills. In order to drive the hilly domestic roads, power performance including vehicle climbing ability should be improved. In order to improve the power performance and the climbing capacity of small electric vehicles, the capacity of the motor should be increased. However, when the performance of the motor is improved, the weight of the motor becomes heavy and the price competitiveness is likely to decrease. In addition, in order to operate a high-performance motor, the power consumption of the battery is rapidly increased, so various problems must be solved. In order to commercialize a small electric vehicle for one or two people who do not emit harmful exhaust gas to the human body in a hilly domestic terrain, it is effective to have a separate transmission system. In this study, we were conducted dynamometer test to produce a continuously variable transmission(CVT) system prototype using a spring that can be applied to a small electric vehicle and to install a CVT system prototype manufactured in a small electric vehicle. The dynamometer test results showed that the maximum speed performance, acceleration performance, and climbing performance were improved.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.4
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• pp.53-63
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• 2009

This work proposes a 10b 100MS/s 27.2mW $0.8mm^2$ 0.18um CMOS ADC for WLAN such as an IEEE 802.11n standard. The proposed ADC employs a three-stage pipeline architecture and minimizes power consumption and chip area by sharing as many circuits as possible. Two multiplying DACs share a single amplifier without MOS switches connected in series while the shared amplifier does not show a conventional memory effect. All three flash ADCs use only one resistor ladder while the second and third flash ADCs share all pre-amps to further reduce power consumption and chip area. The interpolation circuit employed in the flash ADCs halves the required number of pre-amps and an input-output isolated dynamic latch reduces the increased kickback noise caused by the pre-amp sharing. The prototype ADC implemented in a 0.18um n-well 1P6M CMOS process shows the DNL and INL within 0.83LSB and 1.52LSB at 10b, respectively. The ADC measures an SNDR of 52.1dB and an SFDR of 67.6dB at a sampling rate of 100MS/s. The ADC with an active die area of $0.8mm^2$ consumes 27.2mW at 1.8V and 100MS/s.

• Journal of KIISE:Computer Systems and Theory
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• v.34 no.8
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• pp.367-376
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• 2007

In this paper, we introduce an application-specific and adaptive power management technique for portable systems that support dynamic voltage scaling (DVS). We exploit both the idle time of multitasking systems running soft real-time tasks as well as memory- or CPU-bound code regions. Detailed power and execution time profiles guide an adaptive power manager (APM) that is linked to the operating system. A post-pass optimizer marks candidate regions for DVS by inserting calls to the APM. At runtime, the APM monitors the CPU's performance counters to dynamically determine the affinity of the each marked region. for each region, the APM computes the optimal voltage and frequency setting in terms of energy consumption and switches the CPU to that setting during the execution of the region. Idle time is exploited by monitoring system idle time and switching to the energy-wise most economical setting without prolonging execution. We show that our method is most effective for periodic workloads such as video or audio decoding. We have implemented our method in a multitasking operating system (Microsoft Windows CE) running on an Intel XScale-processor. We achieved up to 9% of total system power savings over the standard power management policy that puts the CPU in a low Power mode during idle periods.

• Journal of Institute of Control, Robotics and Systems
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• v.21 no.12
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• pp.1178-1184
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• 2015

In conventional robotics, charge-coupled device (CCD) and complementary metal-oxide-semiconductor (CMOS) cameras have been utilized for acquiring vision information. These devices have problems, such as narrow optic angles and inefficiencies in visual information processing. Recently, biomimetic vision sensors for robotic applications have been receiving much attention. These sensors are more efficient than conventional vision sensors in terms of the optic angle, power consumption, dynamic range, and redundancy suppression. This paper presents recent research trends on biomimetic vision sensors and discusses future directions.

• KSII Transactions on Internet and Information Systems (TIIS)
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• v.10 no.9
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• pp.4108-4122
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• 2016

To address challenges of an unprecedented growth in mobile data traffic, the ultra-dense network deployment is a cost efficient solution to off-load the traffic over other small cells. However, the real traffic is often much lower than the peak-hour traffic and certain small cells are superfluous, which will not only introduce extra energy consumption, but also impose extra interference onto the radio environment. In this paper, an elastic energy efficient cell management scheme is proposed based on flow scheduling among multi-layer ultra-dense cells by a SDN controller. A significant power saving was achieved by a cell-level energy manager. The scheme is elastic for energy saving, adaptive to the dynamic traffic distribution in the office or campus environment. In the end, the performance is evaluated and demonstrated. The results show substantial improvements over the conventional method in terms of the number of active BSs, the handover times, and the switches of BSs.

• Proceedings of the Korean Society for Noise and Vibration Engineering Conference
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• 2007.11a
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• pp.1272-1275
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• 2007

The HDD (hard disk drive) using Load/Unload (L/UL) technology includes the benefits which are increased areal density, reduced power consumption and improved shock resistance than those of contact-start-stop (CSS). Dynamic L/UL has been widely used in portable hard disk drive and will become the key technology for developing the small form factor hard disk drive. Main design objectives of the L/UL mechanisms are no slider-disk contact or no media damage even with contact during L/UL, and a smooth and short load and unload process. In this paper, we focus on state matrix, pitch static attitude (PSA), roll static attitude (RSA), loading/unloading contour (LC/ULC), impact force and contact. Stability of slider is mainly determined by PSA and RSA. State matrix by PSA and RSA is also important indicator. Therefore we analyze state matrix of SFF HDD suspension through the LC/ULC.

• Proceedings of the Materials Research Society of Korea Conference
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• 2003.11a
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• pp.128-128
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• 2003

Electrochromism (EC) is defined as a phenomenon in which a change in color takes place in the presence of an applied voltage. Because of their low power consumption, high coloration efficiency, EC devices have a variety of potential applications in smart windows, mirror, and optical switching devices. An EC devices generally consist of a transparent conducting layer, electrochromic cathodic and anodic coloring materials and an ion conducting electrolyte. EC has been widely studied in transition metal oxides(e.g., WO$_3$, NiO, V$_2$O$\sub$5/) Among these materials, WO$_3$ is a most interesting material for cathodic coloration materials due to its lush coloration efficiency (CE), large dynamic range, cyclic reversibility, and low cost material. WO$_3$ films have been prepared by a variety of methods including vacuum evaporation, chemical vapor deposition, electrodeposition process, sol-gel synthesis, sputtering, and laser ablation. Sol-gel process is widely used for oxide film at low temperature in atmosphere and requires lower capital investment to deposit large area coating compared to vacuum deposition process.