• Journal of the Korean Vacuum Society
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• v.17 no.1
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• pp.16-22
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• 2008

We studied plasma etching of polycarbonate in $O_2/SF_6$, $O_2/N_2$ and $O_2/CH_4$. A capacitively coupled plasma system was employed for the research. For patterning, we used a photolithography method with UV exposure after coating a photoresist on the polycarbonate. Main variables in the experiment were the mixing ratio of $O_2$ and other gases, and RF chuck power. Especially, we used only a mechanical pump for in order to operate the system. The chamber pressure was fixed at 100 mTorr. All of surface profilometry, atomic force microscopy and scanning electron microscopy were used for characterization of the etched polycarbonate samples. According to the results, $O_2/SF_6$ plasmas gave the higher etch rate of the polycarbonate than pure $O_2$ and $SF_6$ plasmas. For example, with maintaining 100W RF chuck power and 100 mTorr chamber pressure, 20 sccm $O_2$ plasma provided about $0.4{\mu}m$/min of polycarbonate etch rate and 20 sccm $SF_6$ produced only $0.2{\mu}m$/min. However, the mixed plasma of 60 % $O_2$ and 40 % $SF_6$ gas flow rate generated about $0.56{\mu}m$ with even low -DC bias induced compared to that of $O_2$. More addition of $SF_6$ to the mixture reduced etch of polycarbonate. The surface roughness of etched polycarbonate was roughed about 3 times worse measured by atomic force microscopy. However examination with scanning electron microscopy indicated that the surface was comparable to that of photoresist. Increase of RF chuck power raised -DC bias on the chuck and etch rate of polycarbonate almost linearly. The etch selectivity of polycarbonate to photoresist was about 1:1. The meaning of these results was that the simple capacitively coupled plasma system can be used to make a microstructure on polymer with $O_2/SF_6$ plasmas. This result can be applied to plasma processing of other polymers.

• Proceedings of the Materials Research Society of Korea Conference
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• 2003.03a
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• pp.88-88
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• 2003

Optical Emission Spectroscopy(OES) is a very important technology for real-time monitoring of plasma in a reactor during dry etching process. OES technology is non-invasive to the plasma process. It can be used to collect information on excitation and recombination between electrons and ions in the plasma. It also helps easily diagnose plasma intensity and monitor end-point during plasma etch processing. We studied high density planar inductively coupled BCl$_3$ and BCl$_3$/Ar plasma with an OES as a function of processing pressure, RIE chuck power, ICP source power and gas composition. The scan range of wavelength used was from 400 nm to 1000 nm. It was found that OES peak Intensity was a strong function of ICP source power and processing pressure, while it was almost independent on RIE chuck power in BCl$_3$-based planar ICP processes. It was also worthwhile to note that increase of processing pressure reduced negatively self-induced dc bias. The case was reverse for RIE chuck power. ICP power and gas composition hardly had influence on do bias. We will report OES results of high density planar inductively coupled BCl$_3$ and BCl$_3$/Ar Plasma in detail in this presentation.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2008.06a
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• pp.168-168
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• 2008

Dimension of a transistor has rapidly shrunk to increase the speed of device and to reduce the power consumption. However, it is accompanied with several problems like direct tunneling through the gate dioxide layer and low conductivity characteristic of poly-Si gate in nano-region. To cover these faults, study of new materials is urgently needed. Recently, high dielectric materials like $Al_2O_3$, $ZrO_2$, and $HfO_2$ are being studied for equivalent oxide thickness (EOT). However, poly-Si gate is not compatible with high-k materials for gate-insulator. Poly Si gate with high-k material has some problems such as gate depletion and dopant penetration problems. Therefore, new gate structure or materials that are compatible with high-k materials are also needed. TiN for metal/high-k gate stack is conductive enough to allow a good electrical connection and compatible with high-k materials. According to this trend, the study on dry etching of TiN for metal/high-k gate stack is needed. In this study, the investigations of the TiN etching characteristics were carried out using the inductively coupled $BCl_3$-based plasma system and adding $Cl_2$ gas. Dry etching of the TiN was studied by varying the etching parameters including $BCl_3$/Ar gas mixing ratio, RF power, DC-bias voltage to substrate, and $Cl_2$ gas addition. The plasmas were characterized by optical emission spectroscopy analysis. Scanning electron microscopy was used to investigate the etching profile.

• JSTS:Journal of Semiconductor Technology and Science
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• v.4 no.3
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• pp.217-221
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• 2004

[ $CO_2$ ]laser ablation rates for bulk 4H-SiC substrates and GaN/AIN/SiC templates in the range 229-870 ${\mu}m.min^{-1}$ were obtained for pulse energies of 7.5-30 mJ over diameters of 50·500 ${\mu}m$ with a Q-switched pulse width of ${\sim}30$ nsec and a pulse frequency of 8 Hz. The laser drilling produces much higher etch rates than conventional dry plasma etching (0.2 - 1.3 ${\mu}m/min$) making this an attractive maskless option for creating through-wafer via holes in SiC or GaN/AlN/SiC templates for power metal-semiconductor field effect transistor applications. The via entry can be tapered to facilitate subsequent metallization by control of the laser power and the total residual surface contamination can be minimized in a similar fashion and with a high gas throughput to avoid redeposition. The sidewall roughness is also comparable or better than conventional via holes created by plasma etching.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.24 no.2
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• pp.156-161
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• 2011

The present study introduces a novel wet etching technique for nanostructure fabrications which usually requires low surface roughness. Using the current method, acquired profiles were smooth even in the nanoscale, which cannot be easily achieved with conventional wet or dry etching methods. As one of the most popular single crystal silicon etchant, potassium hydroxide (KOH) solution was used as a base solvent and two additives, antimony trioxide (Sb2O3) and ethyl alcohol were employed in. Four experimental parameters, concentrations of KOH, Sb2O3, and ethyl alcohol and temperature were optimized at 60 wt.%, 0.003 wt.%, 10 v/v%, and $23^{\circ}C$, respectively. Effects of additives in KOH solution were investigated on the profiles in both (110) and (111) planes of single crystal silicon wafer. The preliminary results show that additives play a critical role to decrease etch rate significantly down to ~2 nm/min resulting in smooth side wall profiles on (111) plane and enhanced surface roughness.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2001.07a
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• pp.275-278
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• 2001

Ferroelectric PZT thin films were fabricated on the RuO$_2$/Pt, Pt bottom electrode with a PZT(53/47) metal alkoxide solutions. All PZT thin films showed a uniform grain structure without the presence of rosette structure. The PZT thin films were etched as a function of Cl$_2$/Ar and additive CF$_4$ into Cl$_2$(80%)/Ar(20%). The etch rates of PZT thin films were 1970 ${\AA}$/min at 30 % additive CF$_4$ into Cl$_2$(80%)/Ar(20%). The remanent polarization and leakage current density in PZT thin film on the RuO$_2$/Pt were 64.2 ${\mu}$C/cm$^2$, 1.4${\times}$10$\^$-6/ respectively.

• 한국정보디스플레이학회:학술대회논문집
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• 2008.10a
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• pp.1097-1100
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• 2008

We demonstrate that the performance of amorphous indium-gallium-zinc-oxide (IGZO) thin-film transistors (TFT) can be optimized by controlling the interfaces between IGZO and sandwiching insulators and by proper deposition of IGZO layer. Specifically, contact and channel resistances are decreased by reducing IGZO bulk resistance and optimizing dry-etch process, respectively. Field-effect mobility ($\mu_{FE}$) and subthreshold gate swing (S) are further enhanced by fine-tuning IGZO deposition condition.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2002.07a
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• pp.375-378
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• 2002

We investigated the reduction of etching damage by additive O$_2$ in etching gas and recovery of etching damage by O$_2$ annealing. The PZT thin films were etched using additive Ar or O$_2$ into Cl$_2$/CF$_4$ gas mixing ratio of 8/2. In order to recover ferroelectric properties of PZT thin films after etching, the etched PZT thin films were annealed at 600 C in O$_2$ atmosphere for 10 min. The remanent polarization is decreased seriously and fatigue is accelerated in the PZT sample etched in Ar/(C1$_2$+CF$_4$) plasma, whereas these characteristics are improved in O$_2$/(Cl$_2$/CF$_4$). From x-ray photoelectron spectroscopy (XPS) analysis, the intensities of Pb-O, Zr-O and Ti-O peaks are changed and the etch byproducts such as metal chloride and metal fluoride are reduced by O$_2$ annealing. From electron probe micro analyzer (EPMA) and auger electron spectroscopy(AES), O$_2$ vacancy is observed after etching. In x-ray diffraction (XRD), the structure damage in the additive O$_2$ into C1$_2$/CF$_4$ is reduced and the improvement of ferroelectric behavioral annealed sample is consistent with the increase of the (100) and (200) PZT peaks.

• 한국정보디스플레이학회:학술대회논문집
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• 2007.08a
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• pp.145-148
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• 2007

The authors report on the fabrication of thin film transistors (TFTs) that use amorphous indium-gallium-zinc oxide (a-IGZO) channel and have the channel length (L) and width (W) patterned by dry etching. To prevent the plasma damage of active channel, a 100-nm-thckness $SiO_{x}$ by PECVD was adopted as an etch-stopper structure. IGZO TFT (W/L=10/50${\mu}m$) fabricated on glass exhibited the high performance mobility of $35.8\;cm^2/Vs$, a subthreshold gate voltage swing of $0.59V/dec$, and $I_{on/off}$ of $4.9{\times}10^6$. In addition, 4.1” transparent QCIF active-matrix organic light-emitting diode display were successfully fabricated, which was driven by a-IGZO TFTs.

• Journal of the Semiconductor & Display Technology
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• v.17 no.3
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• pp.36-40
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• 2018

We have developed a nonlithographic patterning technique using polystyrene nanoparticles to form nanonet channel structures which is promising for high-performance TFT applications. Nanoparticles assisted patterning (NAP) is a technique to form uniform nano-patterns by applying lift-off and dry etch process. Oxygen plasma treatment was used to control the diameters of nanonet hole size to realize a branch width down to 100 nm. NAP technology can be very promising to fabricate nanonet structure with advantages of lower manufacturing cost and large-area patterning capability.