High -Rate Laser Ablation For Through-Wafer Via Holes in SiC Substrates and GaN/AlN/SiC Templates

  • Kim, S. (Department of Chemical Engineering, University of Florida) ;
  • Bang, B.S. (Department of Chemical Engineering, University of Florida) ;
  • Ren, F. (Department of Chemical Engineering, University of Florida) ;
  • d'Entremont, J. (Lenox Laser Inc.) ;
  • Blumenfeld, W. (Lenox Laser Inc.) ;
  • Cordock, T. (Lenox Laser Inc.) ;
  • Pearton, S.J. (Department of Material Science and Engineering University of Florida)
  • Published : 2004.09.30

Abstract

[ $CO_2$ ]laser ablation rates for bulk 4H-SiC substrates and GaN/AIN/SiC templates in the range 229-870 ${\mu}m.min^{-1}$ were obtained for pulse energies of 7.5-30 mJ over diameters of 50·500 ${\mu}m$ with a Q-switched pulse width of ${\sim}30$ nsec and a pulse frequency of 8 Hz. The laser drilling produces much higher etch rates than conventional dry plasma etching (0.2 - 1.3 ${\mu}m/min$) making this an attractive maskless option for creating through-wafer via holes in SiC or GaN/AlN/SiC templates for power metal-semiconductor field effect transistor applications. The via entry can be tapered to facilitate subsequent metallization by control of the laser power and the total residual surface contamination can be minimized in a similar fashion and with a high gas throughput to avoid redeposition. The sidewall roughness is also comparable or better than conventional via holes created by plasma etching.

Keywords

References

  1. J C J Verhoeven, J K M Jansen, R M M Mattheij and W R Smith, Mathematical and Computer Modelling 37 419(2003) https://doi.org/10.1016/S0895-7177(03)00017-7
  2. J B Casady, E D Luckowski, M Bozack, D Sheridan, R W Johnson, J R Williams, J Electrochem Soc, 143 1750 (1996) https://doi.org/10.1149/1.1836711
  3. J B Casady, A K Agarwal, S Seshadri, R R Siergiej, L B Rowland, M F MacMillan, D C Sheridan, P A Sanger, C D Brandt. Solid-State Electronics 42 2165 (1998) https://doi.org/10.1016/S0038-1101(98)00212-3
  4. R Singh, J A Cooper, M R Melloch, J W Palmour, T P Chow, IEEE Trans on Electron Dev 49 665 (2002) https://doi.org/10.1109/16.992877
  5. A P Zhang, L B Rowland, E B Kaminsky, J W Kretchmer. R A Beaupre, J L Garrett, J B Tucker, B J Edward, J Foppes, A F Allen, Solid-State Electron 47 821 (2003) https://doi.org/10.1016/S0038-1101(02)00396-9
  6. S Thomas III and J J Brown, in Handbook of Advanced Plasma Processing Techniques, ed R J Shul and S J Pearton (Springer, Berlin 2000)
  7. P H Yih, A J Steckl, J Electrochem Soc 142 2853 (1995) https://doi.org/10.1149/1.2050105
  8. P Leerungnawarat, D C Hays, H Cho, S J Pearton, R M Strong, C M Zetterling, and M Ostling, J Vac Sci Technol B 17 2050 (1999) https://doi.org/10.1116/1.590870
  9. S Tanaka, K Rajanna, T Abe, and M Esashi, J Vae Sci Technol B 19 2173 (2001) https://doi.org/10.1116/1.1418401
  10. B Li, L Cao and J H Zhao, Appl Phys Lett 73 653 (1998) https://doi.org/10.1063/1.121937
  11. J R Flemish, K Xie and J H Zhao, Appl Phys Lett 64 2315 (1994) https://doi.org/10.1063/1.111629
  12. F A Khan and I Adesida, Appl Phys Lett 75 2268 (1999) https://doi.org/10.1063/1.124986
  13. H Cho, P Leerungnawarat, D C Hays, and S J Pearton, S N G Chu, R M Strong, C-M Zetterling and M Ostling and F Ren, Appl Phys Lett 76 739 (2000) https://doi.org/10.1063/1.125879
  14. P Chabert, N Proust, J Perrin and R W Boswell, Appl Phys Lett 76 2310 (2000) https://doi.org/10.1063/1.126329
  15. J J Wang, E S Lambers, S J Pearton, M Ostling, C -M Zetterling, J M Grow, F Ren, and R J Shul, J Vac Sci Technol A 16 2204 (1998) https://doi.org/10.1116/1.581328
  16. G F McLane and J R Flemish, Appl Phys Lett 68 3755 (1996) https://doi.org/10.1063/1.115996
  17. F A Khan, L Zhou, V Kumar, J Electrochem Soc 149 G420 (2002) https://doi.org/10.1149/1.1482059
  18. I P Leerungnawarat, K P Lee, S J Pearton, F Ren, S N G Chu, J Electron Mater 30 202 (2001) https://doi.org/10.1007/s11664-001-0016-0
  19. see for example, R J Shul (ed) Handbook of Advanced Plasma Processing Techniques (Springer, Berlin, 2000)