• 전력전자학회:학술대회논문집
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• 전력전자학회 2002년도 전력전자학술대회 논문집
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• pp.163-165
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• 2002

LDD구조를 가진 LDMOS 전력소자의 LDD영역과 채널영역변화에 의한 전기적 특성을 비교 조사하였다. MEDICI 시뮬레이션 tool을 이용하여 hot-carrier전류의 특성, ON 저항의 변화, breakdown 전압의 특성과 switch transient 특성을 조사하였다. Gate-drain 사이의 불순물도핑 영역 및 농도에 따른 소자의 특성해석은 LDD구조를 가진 LDMOS가 hot-carrier resistance 및 전력소모 관점에서 우수한 특성을 나타낼 것으로 사료된다

• 한국정보디스플레이학회:학술대회논문집
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• 한국정보디스플레이학회 2009년도 9th International Meeting on Information Display
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• pp.1197-1199
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• 2009

Self-alignment for the fabrication of printed thin film transistors has become of great interest because of the resolution and registration limits of printing technologies. In this work, self-patterning and selfregistration processes are introduced, which do not need surface energy patterning and the resulting minimum gate channel length could be down to $11.2{\mu}m$ with the sheet resistance of 2.6 ${\Omega}/{\square]$ for the source and drain electrodes.

• 조명전기설비학회논문지
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• 제27권3호
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• pp.55-64
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• 2013

In this paper, a new topology which can add a small reactor in series to a condenser-bank type reactive power compensator to limit current is proposed. And also the proposed topology can add or remove a power condenser safely without any addition of inrush-current suppression resistance. The proposed method tests variable resistance of the drain source of a switching device which is controlled by gate voltage in a two-way switch with a diode rectifier and FET switch. In other words, the proposed method is a inrush-current suppression method with the structure of variable resistance. In particular, the proposed method creates smooth current without any resonance in inrush-current as well as is not limited by the time of switch on and off.

• 한국정보디스플레이학회:학술대회논문집
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• 한국정보디스플레이학회 2005년도 International Meeting on Information Displayvol.II
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• pp.1413-1415
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• 2005

The OTFT performance depends strongly on the interfacial properties between an organic semiconductor and ${\alpha}$ metal electrode. The contact resistance is critical to the current flow in the device. The contact resistance arises mainly from the Schottky barrier formation due to the work function difference between the semiconductor and electrodes. We doped pentacene/source-drain interfaces with $F_4TCNQ$ (2,3,5,6-Tetrafluoro-7,7,8,8-tetracyanoquinodimethane), resulting in p-doped region at the SD contacts, in order to solve this problem. We found that the mobility increased and the threshold voltage decreased.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2002년도 하계종합학술대회 논문집(2)
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• pp.217-220
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• 2002

In this paper, we have investigated electronical chara-cteristics of power LDMOSFETS having different ex-tended gate lengths(1.B${\mu}{\textrm}{m}$, 2.4${\mu}{\textrm}{m}$, 3.O${\mu}{\textrm}{m}$) in the temperature range of 300k-500K. The results of this study indicate that on-resistance, breakdown voltage increase with temperature. and drain current, threshold voltage, transconductance decrease with temperature. Particular the facts, we observed that Le is the more increase, on-resistance is the more decrease. because every conditions are fixed normal states, only change the Le. As a result, Ron/BV, known for a figure of merit of power device, increase with temperature.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2003년도 하계종합학술대회 논문집 II
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• pp.1057-1060
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• 2003

This paper is about the optimized fabricated parameter in the EDMOSFET(Extended drain MOSFET) with a various temperature. As we know, the two important factors of EDMOSFET parameters are breakdown voltage and on Resistance. So, we have aims of the power EDMOSFET design to have high breakdown voltage and low on resistance. Thus in this paper, we will show the figure of merit in LDMOS (BV/Ron) in accordance with increase in temperature(300K-500K, step:50K), and measure electronic characteristics of power EDMOSFET. As a result, the important factors in design of EDMOS are temperature and Lg.

• 한국지반공학회지:지반
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• 제10권3호
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• pp.33-40
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• 1994

The effects of smear and well resistance should be taken into account for the design of sand drains. Practically, simple design, which employs the method using 112 reduced diameter of drains or assuming the coefficient of consolidation in horizontal direction equals to that in vertical direction, based on the theory neglecting these effects, has been used. In this study, the reliability of existing simple design methods as well as the influences of smear and well resistance was investigated with the equations proposed by Hansbo and Onoue. It is shown that the consolidation time is chiefly governed by the effect of smear for drains with highly permeable sands. For general soil condition and placing type of sand drain, consolidation time is underestimated for simple design wi어. 1/2 reduced diameter of drains, and it is overestimated for that with the assumption that the coefficient of consolidation in horizontal direction equals to that in vertical direction. Through the investigations on different reduced diameter, it was shown that simple design with 1/4 reduced diameter of drains yielded the reliable results with errors less than 6%.

• 한국전기전자재료학회논문지
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• 제27권8호
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• pp.501-504
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• 2014

This paper was developed and described core-process to implement low on resistance which was the most important characteristics of SJ (super junction) MOSFET. Firstly, using process-simulation, SJ MOSFET optimal structure was set and developed its process flow chart by repeated simulation. Following process flow, gate level process was performed. And source and drain level process was similar to genral planar MOSFET, so the process was the same as the general planar MOSFET. And then to develop deep trench process which was main process of the whole process, after finishing photo mask process, we developed deep trench process. We expected that developed process was necessary to develop SJ MOSFET for automobile semiconductor.

• 대한전기학회:학술대회논문집
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• 대한전기학회 1993년도 하계학술대회 논문집 B
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• pp.1286-1288
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• 1993

An analytical method for the optimum design of the minimum die size in power MOSFETs is presented. The proposed methodology considers the thermal resistance of the package and gives the minimum die area for desired drain current levels. The results are compared with experimental data and it is found that the die size mar be reduced if it is designed according to the proposed design procedure.

• 한국전기전자재료학회논문지
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• 제31권1호
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• pp.6-10
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• 2018

Ni germanide (NiGe) is a promising alloy material with small contact resistance at the source/drain (S/D) of Ge MOSFETs. However, it is necessary to reduce the specific contact resistance between NiGe and the doped Ge S/D region in high-performance MOSFETs. In this study, a novel method is proposed to reduce the specific contact resistance between NiGe and p-type Ge (p-Ge) using a Tb interlayer. The specific contact resistance between NiGe and p-Ge was successfully decreased with the introduction of the Tb interlayer. To investigate the mechanism behind the reduction in the specific contact resistance, the elemental distribution and crystalline structure of NiGe were analyzed using secondary ion mass spectroscopy and X-ray diffraction. It is likely that the reduction in specific contact resistance was caused by an increase in the concentration of boron in the space between NiGe and p-Ge due to the influence of the Tb interlayer.