Proceedings of the KIEE Conference (대한전기학회:학술대회논문집)
- 1993.07b
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- Pages.1286-1288
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- 1993
A Design Methodology for The Minimum DIE Area of Power MOSFET's Considering Thermal Resistance of the Package
Package 의 열저항을 고려한 전력용 MOSFET의 최소 DIE 면적 설계
- Kim, Soo-Seong (Seoul National University) ;
- Kim, Il-Jung (Seoul National University) ;
- Choi, Yearn-Ik (Ajou University) ;
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Han, Min-Koo
(Seoul National University)
- Published : 1993.07.18
Abstract
An analytical method for the optimum design of the minimum die size in power MOSFETs is presented. The proposed methodology considers the thermal resistance of the package and gives the minimum die area for desired drain current levels. The results are compared with experimental data and it is found that the die size mar be reduced if it is designed according to the proposed design procedure.
Keywords