• The Transactions of The Korean Institute of Electrical Engineers
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• v.68 no.1
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• pp.90-97
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• 2019

The charge redistribution digital-to-analog converter(CR-DAC) is often used for successive approximation register analog-to-digital converter(SAR ADC) that requiring low power consumption and small circuit area. However, CR-DAC is required 2 to the power of N unit capacitors to generate reference voltage for successive approximation of the N-bit SAR ADC, and many unit capacitors occupy large circuit area and consume more power. In order to improve this problem, this paper proposes SAR ADC using series capacitor DAC. The series capacitor DAC is required 2(1+N) unit capacitors to generate reference voltage for successive approximation and charges only two capacitors of the reference generation block. Because of these structural characteristics, the SAR ADC using series capacitor DAC can reduce the power consumption and circuit area. Proposed SAR ADC was designed in CMOS 180nm process, and at 1.8V supply voltage and 500kS/s sampling rate, proposed 6-bit SAR ADC have signal-to-noise and distortion ratio(SNDR) of 36.49dB, effective number of bits(ENOB) of 5.77-bit, power consumption of 294uW.

• Biomedical Science Letters
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• v.30 no.3
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• pp.131-136
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• 2024

In this investigation, a novel design for a well-plate structure was created to optimize antigen-antibody reactions. The main objective during the development process was to enhance the internal structure of the well plate and increase the surface area. To improve efficiency, the newly designed well-plate was conical in shape and featured internal protrusions, or fins, which increased the surface area per unit volume by 1.45 times compared to standard plates. The performance of the newly developed well plate was assessed using a sandwich CLEIA system, which demonstrated a detection limit approximately 2.5 times better than that of commercial products. Additionally, the coefficient of variation (CV%) was superior to that of commercial products, with inter-assay CV(%) ≤ 11 and intra-assay CV(%) ≤ 9, compared with inter-assay CV(%) ≤ 15 and intra-assay CV(%) ≤ 10 for commercial products. Furthermore, the newly designed well plate demonstrated higher reaction efficiency, even with smaller sample volumes (25~50 µL) compared to the 50~100 µL typically required by commercial well plates. The incorporation of fine patterns increases the number of active sites available for interaction with the samples, thereby significantly enhancing the reaction sensitivity and overall performance.

• Journal of IKEEE
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• v.2 no.2 s.3
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• pp.309-315
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• 1998

This paper describes an 8b 52 MHz CMOS subranging analog-to-digital converter (ADC) for Integrated Services Digital Network (ISDN) applications. The proposed ADC based on the improved time-interleaved architecture removes the holding time which is typically observed in the conventional double-channel subranging ADCs to increase throughput rate. Moreover, the ADC employs the interpolation technique in the back-end subranging ADCs far residue signal processing to minimize die area and power consumption. The fabricated and measured prototype ADC in a 0.8 um n-well double-poly double-metal CMOS process typically shows a 52 MHz sampling rate at a 5 V supply voltage with 230 mW, and a 40 MHz sampling rate at a 3 V power supply with 60 mW power consumption.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.39 no.4
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• pp.25-35
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• 2002

This work describes an 8b 200MHz time-interleaved subranging analog-to-digital converter (ADC) based on a single-poly digital CMOS process. Two fine ADCs for lower digital bits of the proposed ADC employ a time-sharing double-channel architecture to increase system speed and a new reference voltage switching scheme to reduce settling time of the reference voltages and chip area. The proposed intermeshed resistor string, which generates reference voltages for fine ADCs, improves linearity and settling time of the reference voltages simultaneously. The proposed sample- and-hold amplifier(SHA) is based on a highly linear common-drain amplifier and passive differential circuits to minimize power consumption and chip area with 8b accuracy and employs input dynamic common mode feedback circuits for high dynamic performance at a 200MHz sampling rate. A new encoding circuit in a coarse ADC simplifies the signal processing between the coarse ADC and two successive fine ADCs.

• Journal of IKEEE
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• v.19 no.3
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• pp.342-348
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• 2015

High speed implementation of digital filters is required in high data rate applications such as hard-wired wide band modem and high resolution video codec. Since the critical path of the digital filter is the MAC (multiplication and accumulation) circuit, the filter coefficient with sparse non-zero bits enables high speed implementation with adders of low hardware cost. Compressive sensing has been reported to be very successful in sparse representation and sparse signal recovery. In this paper a filter design method for digital FIR filters with CSD (canonic signed digit) coefficients using compressive sensing technique is proposed. The sparse non-zero signed bits are selected in the greedy fashion while pruning the mistakenly selected digits. A few design examples show that the proposed method can be utilized for designing sparse CSD coefficient digital FIR filters approximating the desired frequency response.

• Journal of the Korea Society of Computer and Information
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• v.15 no.2
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• pp.109-117
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• 2010

Digital watermarking has drawn extensive attention for protecting digital contents from unauthorized copying. This paper proposes a new watermarking scheme in frequency domain for copyright protection of digital audio. In our proposed watermarking system, the original audio is segmented into non-overlapping frames. Watermarks are then embedded into the selected prominent peaks in the magnitude spectrum of each frame. Watermarks are extracted by performing the inverse operation of watermark embedding process. Simulation results indicate that the proposed scheme is robust against various kinds of attacks such as noise addition, cropping, resampling, re-quantization, MP3 compression, and low pass filtering. Our proposed watermarking system outperforms Cox's method in terms of imperceptibility, while keeping comparable robustness with the Cox's method. Our proposed system achieves SNR (signal-to-noise ratio) values ranging from 20 dB to 28 dB. This is in contrast to Cox's method which achieves SNR values ranging from only 14 dB to 23 dB.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.45 no.7
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• pp.32-37
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• 2008

Satellite communication systems including the DVB-S2 (Digital Video Broadcasting - Satellite Version 2) system require operations under low signal-to-noise ratio (SNR) and large frequency offset values, and the initial frame synchronization process necessitates a robust correlation method. While a variety of conventional correlation structures exist for the initial synchronization, each method has different characteristics and performance in different channel environments. In this paper, we propose new correlation methods which exhibit enhanced performance in low SNR and large frequency offsets, and analyze their performance. The proposed methods use the magnitude sum and vector sum of extended differential correlation values, to maximize the correlation between the received signal and the synchronization sequence by using the spanned differential correlation result. The magnitude sum correlation method has better performance compared to conventional methods including the approximated ML (Maximum likelihood) method for SNR values below 4 dB with or without frequency offsets. The vector sum correlation method has improved performance over the magnitude sum method for channels with relatively small frequency offsets.

• Journal of Digital Convergence
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• v.16 no.12
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• pp.459-466
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• 2018

Gendered innovations is a term used by policy makers and academics to refer the process of creating better research and development (R&D) for both men and women. In this paper, we analyze the literatures in image and speech signal processing that can be used in ICT, examine the importance of gendered innovations through case study. Therefore the latest domestic and foreign literature related to image and speech signal processing based on gender research is searched and a total of 9 papers are selected. In terms of gender analysis, research subjects, research environment, and research design are examined separately. Especially, through the case analysis of algorithms of the elderly voice signal processing, machine learning, machine translation technology, and facial gender recognition technology, we found that there is gender bias in existing algorithms, and which leads to gender analysis is required. We also propose a gendered innovations method integrating sex and gender analysis in algorithm development. Gendered innovations in ICT can contribute to the creation of new markets by developing products and services that reflect the needs of both men and women.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.47 no.9
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• pp.1-8
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• 2010

A digital phase wrapping modulation (DPM) open-loop polar transmitter can be efficiently applied to a wideband orthogonal frequency division multiplexing (OFDM) communication system by converting in-phase and quadrature signals to envelope and phase signals and then employing the signal mapping process. This mapping process is very similar to quantization in a general communication system, and when taking into account the error that appears during mapping process, one can replace the coordinates rotation digital computer (CORDIC) algorithm in the coordinate conversion part with the Taylor series approximation method. In this paper, we investigate the application of the Taylor series approximation to the cartesian to polar coordinate conversion part of a DPM polar transmitter for wideband OFDM systems. The conventional approach relies on the CORDIC algorithm. To achieve efficient application, we perform computer simulation to measure mean square error (MSE) of the both approaches and find the minimum approximation order for the Taylor series approximation compatible to allowable error of the CORDIC algorithm in terms of hardware design. Furthermore, comparing the processing speeds of the both approaches in the implementation with FPGA reveals that the Taylor series approximation with lower order improves the processing speed in the coordinate conversion part.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.11
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• pp.6-12
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• 2010

A sigma-delta modulator based class-D audio amplifier is presented. Parallel digital input is serialized to two-bit output by a fourth-order digital sigma-delta noise shaper. The output of the digital sigma-delta noise shaper is applied to a fourth-order analog sigma-delta modulator whose three-level output drives power switches. The pulse density modulated (PDM) output of the power switches is low-pass filtered by an LC-filter. The PDM output of the power switches is fed back to the input of the analog sigma-delta modulator. The first integrator of the analog sigma-delta modulator is a hybrid of continuous-time (CT) and switched-capacitor (SC) integrator. While the sampled input is applied to SC path, the continuous-time feedback signal is applied to CT path to suppress the noise of the PDM output. The class-D audio amplifier is fabricated in a standard $0.13-{\mu}m$ CMOS process and operates for the signal bandwidth from 100-Hz to 20-kHz. With 4-${\Omega}$ load, the maximum output power is 18.3-mW. The total harmonic distortion plus noise and dynamic range are 0.035-% and 80-dB, respectively. The modulator consumes 457-uW from 1.2-V power supply.