Journal of the Institute of Electronics Engineers of Korea SC (전자공학회논문지SC)

The Institute of Electronics and Information Engineers (대한전자공학회)
권호 표지

An 8b 200MHz Time-Interleaved Subranging ADC With a New Reference Voltage Switching Scheme

새로운 기준 전압 인가 방법을 사용하는 8b 200MHz 시간 공유 서브레인징 ADC

  • Published : 2002.07.01
Download PDF
⟨ Previous Next ⟩

Abstract

This work describes an 8b 200MHz time-interleaved subranging analog-to-digital converter (ADC) based on a single-poly digital CMOS process. Two fine ADCs for lower digital bits of the proposed ADC employ a time-sharing double-channel architecture to increase system speed and a new reference voltage switching scheme to reduce settling time of the reference voltages and chip area. The proposed intermeshed resistor string, which generates reference voltages for fine ADCs, improves linearity and settling time of the reference voltages simultaneously. The proposed sample- and-hold amplifier(SHA) is based on a highly linear common-drain amplifier and passive differential circuits to minimize power consumption and chip area with 8b accuracy and employs input dynamic common mode feedback circuits for high dynamic performance at a 200MHz sampling rate. A new encoding circuit in a coarse ADC simplifies the signal processing between the coarse ADC and two successive fine ADCs.

본 논문에서는 단일 폴리 공정을 기반으로 하여 8b 해상도로 200MHz의 고속 동작을 하기 위해 최적화된 시간 공유 서브레인징 ADC(Analog-to-Digital Converter)를 제안한다. 제안하는 ADC는 높은 정확도를 요구하는 하위 ADC에 이중 채널 구조를 적용하여 높은 샘플링 주파수를 보장하였고, 새로운 기준 전압 인가 방식을 적용하여 기준 전압의 빠른 정착 시간을 얻으면서 동시에 칩 면적을 크게 감소시켰다. 기준 전압을 생성하는 저항열에서는 선형성 및 속도 향상을 위해 기존의 인터메쉬드 구조를 보완한 새로운 저항열을 사용하였다. 8 비트 수준의 정밀도에서 면적 및 전력 소모를 최소화하기 위해 공통 드레인(common- drain) 증폭기 구조를 사용하여 샘플-앤-홀드 증폭기(Sample-and-Hold Amplifier：SHA)를 설계하였으며, 입력단에 스위치와 캐패시터로 구성된 동적 공통 모드 궤환 회로(Dynamic Common Mode Feedback Circuit)를 사용하여 SHA의 동적 동작 범위(dynamic range)를 증가시켰다. 동시에 상위 ADC와 하위 ADC간의 신호 처리를 단순화시키기 위해 상위 ADC에 새로운 인코딩 회로를 제안하였다.

Keywords

References

  1. K. Bult, 'Analog Broadband Communication Circuits in Pure Digital Deep Sub-Micron CMOS,' in ISSCC Dig. Tech. Papers, Feb. 1999, pp. 76-77 https://doi.org/10.1109/ISSCC.1999.759110
  2. K. Bult and A. Buchwald, 'An Embedded 240-mW 10-b 50-MS/s CMOS ADC in 1-mm2,' IEEE J. Solid-State Circuits, vol. 32, pp. 1887-1895, Dec. 1997 https://doi.org/10.1109/4.643647
  3. B.P Brant and J. Lutsky, 'A 74mW 10-b 20-MSPS CMOS subranging ADC with 9.5 effective bits at nyquist,' IEEE J. Solid-State Circuits, vol. 34, pp. 1788-1795, Dec. 1999 https://doi.org/10.1109/4.808903
  4. A. G. W. Venes and R. J. van de Plassche, 'An 80MHz 80mW 8b CMOS folding A/D converter with distributed T/H preprocessing,' in ISSCC Dig. Tech. Papers, Feb. 1996, pp. 318-319 https://doi.org/10.1109/ISSCC.1996.488635
  5. K. Y. Kim, N. Kusayanagi, and A. A. Abidi, 'A 10-b, 100-MS/s CMOS A/D Converter,' IEEE J. Solid-State Circuits, vol. 32, pp. 302-311, Mar. 1997 https://doi.org/10.1109/4.557627
  6. K. Nagaraj, H. S. Fetterman, J. Anidjar, S. H. Lewis, and R. G. Renninger, 'A 250-mW, 8-b, 52-Msamples/s parallel-pipelined A/D converter with reduced number of amplifiers,' IEEE J. Solid-State Circuits, vol. 32, pp. 312-320, Mar. 1997 https://doi.org/10.1109/4.557628
  7. N. Fukushima, T. Yamada, N. Kumazawa, Y. Hasegawa, and M. Soneda, 'A CMOS 40MHz 8b 105mW two-step ADC,' in ISSCC Dig. Tech. Papers, Feb. 1989, pp. 14-15 https://doi.org/10.1109/ISSCC.1989.48213
  8. M. Ishikawa and T. Tsukahara, 'An 8-bit 50-MHz CMOS subranging A/D converter with pipelined wide-band S/H,' IEEE J. Solid-State Circuits, vol. 24, pp. 1485-1491, Dec. 1989 https://doi.org/10.1109/4.44983
  9. S. H. Lee, J. W. Moon, S. H. Lee, 'An 8b 52MHz Double-Channel CMOS Subranging A/D Converter for DSL Applications,' IEICE TRANS. ELECTRON., vol. E84-C, no. 4, pp. 470-474, Apr. 2001
  10. R. Wittmann, W. Schardein, B. J. Hosticka, G. Burbach, and J. Arndt, 'Trimless high precision ratioed resistors in D/A and A/D converters,' IEEE J. Solid-State Circuits, vol. 30, no. 8, pp. 935-939, Aug. 1995 https://doi.org/10.1109/4.400436
  11. M. J. M. Pelgrom, 'A 10-b 50-MHz CMOS D/A converter with 75-${\Omega}$ buffer,' IEEE J. Solid-State Circuits, vol. 25, no. 8, pp. 1347-1353, Dec. 1990 https://doi.org/10.1109/4.62178
  12. B. Razavi, 'Principles of Data Conversion System Design,' IEEE Press, Piscataway, New Jersey, 1995
  13. Y. T. Wang and B. Razavi, 'An 8-bit 150-MHz CMOS A/D Converter,' IEEE J. Solid-State Circuits, vol. 35, no. 3, pp. 308-317, Mar. 2000 https://doi.org/10.1109/4.826812
  14. R. C. Taft and M. R. Tursi, 'A 100-MS/s 8-b CMOS subranging ADC with Sustained Parametric Performance from 3.8V Down to 2.2V,' IEEE J. Solid-State Circuits, vol. 36, no. 3, pp. 331-338, Mar. 2001 https://doi.org/10.1109/4.910471
  15. C. L. Portmann and T. H. Y. Meng 'Power-Efficient Metastability Error Reduction in CMOS Flash A/D Converters,' IEEE J. Solid-State Circuits, vol. 31, no. 8, pp. 1132-1140, Aug. 1996 https://doi.org/10.1109/4.508260
  16. I. Mehr and D. Dalton, 'A 500-MSample/s 6-Bit Nyquist-Rate ADC for Disk-Drive Read-Channel Applications,' IEEE J. Solid-State Circuits, vol. 34, no. 7, pp. 912-920, Jul. 1999 https://doi.org/10.1109/4.772405