• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.24 no.9
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• pp.713-717
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• 2011

This paper was carried out design of 600 V GaN power MOSFET Modeling. We decided trench gate type one for design. we carried out device and process simulation with T-CAD tools. and then, we have extracted optimal device and process parameters for fabrication. we have analysis electrical characteristics after simulations. As results, we obtained 600 V breankdown voltage and $0.4\;m{\Omega}cm^2ultra$ low on resistance. At the same time, we carried out field ring simulation for obtaining high voltage.

• Proceedings of the KAIS Fall Conference
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• 2004.06a
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• pp.172-175
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• 2004

This paper analyzes the effects of Ge profiles shape of SiGe heterojunction bipolar transistors (HBT's) for high frequency application. Device simulations using ATLAS/BLAZE for the SiGe HBT with trapezoidal or triangular Ge profile are carried out to optimize the device performance. An HBT with $15\%$ triangular Ge profile shows higher cut-off frequency and DC current gain than that with $19\%$ trapezoidal Ge profile. The cut-off frequency and DC gain are increased from 42GHz to 84GHz and from 200 to 600, respectively. The SiGe HBT has been fabricated using a production CVD reactor.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2003.11a
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• pp.163-166
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• 2003

The electrothermal simulation of high voltage LIGBT(Lateral Insulated Gate Bipolar Transistor) in thin Silicon on insulator (SOI) and Silicon on sapphire (SOS) for thermal conductivity and sink is performed by means of MEDICI. The finite element simulations demonstrate that the thermal conductivity of the buried oxide is an important parameter for the modeling of the thermal behavior of silicon-on-insulator (SOI) devices. In this paper, using for SOI LIGBT, we simulated electrothermal for device that insulator layer with $SiO_2\;and\;Al_2O_3$ at before and after latch up to measured the thermal conductivity and temperature distribution of whole device and verified that SOI LIGBT with $Al_2O_3$ insulator had good thermal conductivity and reliability

• Journal of the Semiconductor & Display Technology
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• v.22 no.4
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• pp.136-141
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• 2023

The continuous shrinking of transistors in integrated circuits leads to difficulties in improving performance, resulting in the emerging transistors such as nanosheet field-effect transistors. In this paper, we propose a TCAD-machine learning framework of nanosheet FETs to model the current-voltage characteristics. Sentaurus TCAD simulations of nanosheet FETs are performed to obtain a large amount of device data. A machine learning model of I-V characteristics is trained using the multi-layer perceptron from these TCAD data. The weights and biases obtained from multi-layer perceptron are implemented in a PSPICE netlist to verify the accuracy of I-V and the DC transfer characteristics of a CMOS inverter. It is found that the proposed machine learning model is applicable to the prediction of nanosheet field-effect transistors device and circuit performance.

• Proceedings of the KIEE Conference
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• 1979.08a
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• pp.160-161
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• 1979

The degradation of image due to the finite size of sensing device has been one of the problems to all of the digital imaging systems. The improvement of the spatial resolution has been attempted by "differential method" with fixed sensor size and finer sampling. The computer simulations were carried out for the cases of PLF system (Parallel Linear Fan-beam) and SR(Stationary Ring) system and the results are presented.

• Proceedings of the KIPE Conference
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• 2000.07a
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• pp.384-387
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• 2000

In this paper Power factor correction circuit of single-phase three-level boost converter is proposed. The advantage of the proposed control scheme for three-level boost converter are low blocking voltage of each power device low THD(Total Harmonic Distortion) and high power factor. The control scheme is based on the current comparator capacitor compensator and region detector, In simulations the proposed system is validated.

• ETRI Journal
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• v.35 no.6
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• pp.1068-1074
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• 2013

This paper proposes an additional forward error correction (FEC) layer to compensate for the defectiveness inherent in the conventional FEC layer in the Long Term Evolution specifications. The proposed additional layer is called a graceful degradation (GD)-FEC layer and maintains desirable service quality even under burst data loss conditions of a few seconds. This paper also proposes a non-delayed decoding (NDD)-GD-FEC layer that is inherent in the decoding process. Computer simulations and device-based tests show a better loss recovery performance with a negligible increase in CPU utilization and occupied memory size.

• 제어로봇시스템학회:학술대회논문집
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• 1996.10b
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• pp.486-489
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• 1996

The objective of this paper is to design a force feedback controller for bilateral control of a master-slave manipulator system. In a bilateral control system, the motion of the master device is followed by the slave one, while the force applied to the slave is reflected on the master. In this paper, a fuzzy logic controllers applied to the system. Using the fuzzy logic controller, the knowledge of the system dynamics is not needed. Simulations and experimental results show the performance of the proposed controller.

• Journal of the Semiconductor & Display Technology
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• v.8 no.4
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• pp.21-24
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• 2009

We investigated a nanoscale inertia sensor based on telescoping carbon nanotubes, using classical molecular dynamics simulations. The position of the telescoping nanotubes is controlled by the centrifugal force exerted by the rotation platform, thus, position shifts are determined by the capacitance between carbon nanotubes and the electrode, and the operating frequency of the carbon nanotube oscillator. This measurement system, tracking oscillations of the carbon nanotube oscillator, can be used as the sensor for numerous types of devices, such as motion detectors, accelerometers and acoustic sensors.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.32A no.12
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• pp.159-165
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• 1995

A gate-recessed structure is introduced to SOI MOSFET's in order to increase the source-to-drain breakdown voltage. A significant increase in the breakdown voltage is observed compared with that of a planar single source/drain SOI MOSFET without inducing the appreciable reduction of the current drivability. We have analyzed the origin of the breakdown voltage improvement by the substrate current measurements and 2-D device simulations, and shown that the breakdown voltage improvement is caused by the reductions in the impact ionization rate and the parasitic bipolar current gain.