• 제목/요약/키워드: device optimization

검색결과 654건 처리시간 0.03초

Design of a New Haptic Device using a Parallel Mechanism with a Gimbal Mechanism

  • Lee, Sung-Uk;Shin, Ho-Chul;Kim, Seung-Ho
    • 제어로봇시스템학회:학술대회논문집
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    • 제어로봇시스템학회 2005년도 ICCAS
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    • pp.2331-2336
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    • 2005
  • This paper proposes a new haptic device using a parallel mechanism with gimbal type actuators. This device has three legs actuated by 2-DOF gimbal mechanisms, which make the device simple and light by fixing all the actuators to the base. Three extra sensors are placed at passive joints to obtain a unique solution of the forward kinematics problem. The proposed haptic device is developed for an operator to use it on a desktop in due consideration of the size of an average Korean. The proposed haptic device has a small workspace for on operator to use it on a desktop and more sensitivity than a serial type haptic device. Therefore, the motors of the proposed haptic device are fixed at the base plate so that the proposed haptic device has a better dynamic bandwidth due to a low moving inertia. With this conceptual design, optimization of the design parameters is carried out. The objective function is defined by the fuzzy minimum of the global design indices, global force/moment isotropy index, global force/moment payload index, and workspace. Each global index is calculated by a SVD (singular value decomposition) of the force and moment parts of the jacobian matrix. Division of the jacobian matrix assures a consistency of the units in the matrix. Due to the nonlinearity of this objective function, Genetic algorithms are adopted for a global optimization.

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최적화 기법을 사용한 초소형 카메라 조리개 셔터장치의 성능향상 (The Improvement of Performance in an Ultra small Camera Iris-Shutter Device using Topology Optimization)

  • 박순옥;유정훈
    • 정보저장시스템학회논문집
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    • 제5권2호
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    • pp.53-57
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    • 2009
  • This study is concerned with the design of a camera iris-shutter device for producing force. The camera iris-shutter with yoke should have a smaller size and a bigger magnetic force than the previous model. Since the induced magnetic force operates shutter movement, the magnetic force maximization for a given input current is an important issue. To achieve the goal, new system is designed by the topology optimization method. The design is refined through the design of experiments to find the detail camera iris shutter design satisfying design constraints.

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Theo Jansen Mechanism 기반 보행 기구의 최적 설계를 통한 구동의 안정성 및 속도 확보 (Optimized design of walking device based on Theo Jansen Mechanism for securing stability and speed)

  • 김경훈;김승연
    • EDISON SW 활용 경진대회 논문집
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    • 제5회(2016년)
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    • pp.513-515
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    • 2016
  • There are various walking devices based on Theo Jansen mechanism. And these systems controlled by complicate equations. So we decided to optimize the design of walking device with two points of view. The device is required to ensure stability while maintaining the high speed. To simplify the control system, we applied trigonometric ratio with ideal Jansen trajectory. As a result, we were able to draw the connection between height of barrier and Ground Length (GL). Also we could change traveling distance and Ground Angle Coefficient (GAC) by shifting the position of the joints. Through controlling these parameter, we can analyze stability and speed of the device. Ultimately, we develop the device that can walk more efficiently by the optimization process.

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Optimization of Double Gate Vertical Channel Tunneling Field Effect Transistor (DVTFET) with Dielectric Sidewall

  • WANG, XIANGYU;Cho, Wonhee;Baac, Hyoung Won;Seo, Dongsun;Cho, Il Hwan
    • JSTS:Journal of Semiconductor Technology and Science
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    • 제17권2호
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    • pp.192-198
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    • 2017
  • In this paper, we propose a novel double gate vertical channel tunneling field effect transistor (DVTFET) with a dielectric sidewall and optimization characteristics. The dielectric sidewall is applied to the gate region to reduced ambipolar voltage ($V_{amb}$) and double gate structure is applied to improve on-current ($I_{ON}$) and subthreshold swing (SS). We discussed the fin width ($W_S$), body doping concentration, sidewall width ($W_{side}$), drain and gate underlap distance ($X_d$), source doping distance ($X_S$) and pocket doping length ($X_P$) of DVTFET. Each of device performance is investigated with various device parameter variations. To maximize device performance, we apply the optimum values obtained in the above discussion of a optimization simulation. The optimum results are steep SS of 32.6 mV/dec, high $I_{ON}$ of $1.2{\times}10^{-3}A/{\mu}m$ and low $V_{amb}$ of -2.0 V.

Parametric Analysis and Design Optimization of a Pyrotechnically Actuated Device

  • Han, Doo-Hee;Sung, Hong-Gye;Jang, Seung-Gyo;Ryu, Byung-Tae
    • International Journal of Aeronautical and Space Sciences
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    • 제17권3호
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    • pp.409-422
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    • 2016
  • A parametric study based on an unsteady mathematical model of a pyrotechnically actuated device was performed for design optimization. The model simulates time histories for the chamber pressure, temperature, mass transfer and pin motion. It is validated through a comparison with experimentally measured pressure and pin displacement. Parametric analyses were conducted to observe the detailed effects of the design parameters using a validated performance analysis code. The detailed effects of the design variables on the performance were evaluated using the one-at-a-time (OAT) method, while the scatter plot method was used to evaluate relative sensitivity. Finally, the design optimization was conducted by employing a genetic algorithm (GA). Six major design parameters for the GA were chosen based on the results of the sensitivity analysis. A fitness function was suggested, which included the following targets: minimum explosive mass for the uniform ignition (small deviation), light casing weight, short operational time, allowable pyrotechnic shock force and finally the designated pin kinetic energy. The propellant mass and cross-sectional area were the first and the second most sensitive parameters, which significantly affected the pin's kinetic energy. Even though the peak chamber pressure decreased, the pin kinetic energy maintained its designated value because the widened pin cross-sectional area induced enough force at low pressure.

엇갈림 휜을 갖는 전자기기의 열유동 모델링 및 휜 형상 최적 설계 (Thermal and Flow Modeling and Fin Structure Optimization of an Electrical Device with a Staggered Fin)

  • 김치원;이관수;여문수
    • 설비공학논문집
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    • 제29권12호
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    • pp.645-653
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    • 2017
  • Thermal and flow modeling and fin structure optimization were performed to reduce the weight of an electrical device with a staggered fin. First, a numerical model for thermal and flow characteristics was suggested, and then, the model was verified experimentally. Using the verified model, improvement in cooling performance of the cooling system through the staggered fins was predicted. As a result, 87.5% of total heat generated was dissipated through the cooling fins, and a thermal island was observed in the rotor because of low velocity of the internal air flow through the air gap. In addition, it was confirmed that the staggered fin improves the cooling performance but it also increases the total pressure drop within the cooling system, by maximizing the leading edge effect. Based on this analysis result, the effect of each design parameter on the thermal and flow characteristics was analyzed to select the main optimal design parameters, and multi-objective optimization was performed by considering the cooling performance and the fin weight. In conclusion, the optimized fin structure improved the cooling performance by 7% and reduced the fin weight by 28% without any compromise of the pressure drop.

Joint User Association and Resource Allocation of Device-to-Device Communication in Small Cell Networks

  • Gong, Wenrong;Wang, Xiaoxiang
    • KSII Transactions on Internet and Information Systems (TIIS)
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    • 제9권1호
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    • pp.1-19
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    • 2015
  • With the recent popularity of smart terminals, the demand for high-data-rate transmission is growing rapidly, which brings a new challenge for the traditional cellular networks. Both device-to-device (D2D) communication and small cells are effective to improve the transmission efficiency of local communication. In this paper, we apply D2D communication into a small cell network system (SNets) and study about the optimization problem of resource allocation for D2D communication. The optimization problem includes system scheduling and resource allocation, which is exponentially complex and the optimal solution is infeasible to achieve. Therefore, in this paper, the optimization problem is decomposed into several smaller problems and a hierarchical scheme is proposed to obtain the solution. The proposed hierarchical scheme consists of three steps: D2D communication groups formation, the estimation of sub-channels needed by each D2D communication group and specific resource allocation. From numerical simulation results, we find that the proposed resource allocation scheme is effective in improving the spectral efficiency and reducing the outage probability of D2D communication.

InSb TFT의 제작과 최적화 기법에 의한 파라메타 추출 (Fabrication of InSb TFT and Parameters EXtraction Using Optimization Technique)

  • 김홍배;손상희;곽계달
    • 대한전자공학회논문지
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    • 제24권1호
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    • pp.67-72
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    • 1987
  • InSb TFT is fabricated by the vacuum evaporation method and I-V characteristics are measured. Employing Davidon Fletcher-Powell algorithm, the device parameters are extracted. The current-voltage relations calculated by extracdted parameters are in good agreement with experimental results. It is found that optimization technique may be more simple and accurate than curve fitting method in device parameters extration.

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Quasi-SOI LDMOSFET의 전기적 특성 (Electrical Characteristics of Quasi-SOI LDMOSFET)

  • 정두연;이종호
    • 대한전자공학회:학술대회논문집
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    • 대한전자공학회 2000년도 하계종합학술대회 논문집(2)
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    • pp.234-237
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    • 2000
  • In this paper, a method to implement new Quasi-SOI LDMOSFET is introduced and the electrical characteristics of the device are studied. Key process steps of the device are explained briefly. By performing process and device simulations, electrical characteristics of the device are investigated, with emphasis on the optimization of the tilt angle of p$\^$0/ channel region. The electrical properties of the Quasi-SOI device are compared with those of bulk and SOI devices with the same process parameters. Simulated device characteristics are threshold voltage, off-state leakage current, subthreshold swing, DIBL, output resistance, lattice temperature, I$\_$D/-V$\_$Ds/, and cut-off frequency.

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