• 제목/요약/키워드: current gain

검색결과 1,367건 처리시간 0.032초

InP의 습식식각특성과 InP/lnGaAs HBT의 제작 (Wet etching charicteristics of InP in InP/InGaAs HBTs and their fabrication)

  • 김강대;박재홍;김용규;황성범;송정근
    • 대한전자공학회:학술대회논문집
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    • 대한전자공학회 2002년도 하계종합학술대회 논문집(2)
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    • pp.77-80
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    • 2002
  • In this paper, InP-based HBTs have been optimally designed by numerical simulation and fabricated by the self-aligned process. The structure of HBT was designed in terms of the current gain*f$_{max}$ for the base and f$_{T}$*f$_{max}$ for the collector. The designed structure produced the current gain of about 50 and the cutoff frequency and the maximum oscillation frequency of 87GHz and 2940Hz respectively. In addition, we present a study of the vertical and lateral etching of InP with the mask sides parallel to the principal crystallographic axes, [0101 and (001). This etching characteristics arc used to fabricate self-aligned HBT structures with reduced parasitic effects.s.s.s.

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저압 유기금속기상 성장법에 의한 AlGaAs/GaAs 양자 우물에 델타 도우핑된 채널 FET 특성 (Characteristics of AlGaAs/GaAs Quantum-Well Delta-Doped Channel FET's by Low Pressure Metalorganic Chemical Vapor Deposition)

  • 장경식;정동호;이정수;정윤하
    • 전자공학회논문지A
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    • 제29A권4호
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    • pp.33-37
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    • 1992
  • AlGaAs/GaAs quantum well delta-doped channel FET's have been successfully fabricated using by low-pressure metalorganic chemical vapor deposition(LP-MOCVD). The FET's with a gate dimension of 1.8$\mu$m $\times$ 100$\mu$m have a maximum transconductance of 190 mS/mm and a maximum current density of 425 mA/nm. The devices show extremely broad transconductances with a large voltage swing of 2.4V. The S-parameter measurements have indicated that the current gain and power gain cutoff frequencies of the device were 7 and 15 GHz, respectively. These values are among the best performance reported for GaAs based heterojunction FET's with a similar device geometry.

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Air-Bridge 공정을 이용한 GaAs Power MESFET의 제작 및 특성 연구 (Fabrication and Characteristics of GaAs Power MESFETs Using Air-Bridge Processes)

  • 이일형;김상명;이응호;이진구
    • 전자공학회논문지A
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    • 제32A권12호
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    • pp.136-141
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    • 1995
  • GaAs power MESFETs with 1 .mu.m gate length and an undoped GaAs surface layer on the doped GaAs channel are fabricated using IR(image reversal) and air-birdge processes. And then We have measured and calculated DC and RF characteristics. We have obtained saturation current 107-500 mA (197-255 mA/mm), maximum linear RF output power 111-518.8 mW (204-270 mW/mm), current gain cut-off frequency 7-10 GHz, maximum unilateral transducer power gain 5.7-12.7, and power added efficiencies 37.9-41.2 % from the devices with gate width 0.45-2.2 mm, at 6 GHz.

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직접토크제어 유도전동기 구동 서보시스템을 위한 장치고장 진단 기법 (An Instrument Fault Diagnosis Scheme for Direct Torque Controlled Induction Motor Driven Servo Systems)

  • 이기상;유지수
    • 대한전기학회논문지:시스템및제어부문D
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    • 제51권6호
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    • pp.241-251
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    • 2002
  • The effect of sensor faults in direct torque control(DTC) based induction motor drives is analyzed and a new Instrument fault detection isolation scheme(IFDIS) is proposed. The proposed IFDIS, which operated in real-time, detects and isolates the incipient fault(s) of speed sensor and current sensors that provide the feedback information. The scheme consists of an adaptive gain scheduling observer as a residual generator and a special sequential test logic unit. The observer provides not only the estimate of stator flux, a key variable in DTC system, but also the estimates of stator current and rotor speed that are useful for fault detection. With the test logic, the IFDIS has the functionality of fault isolation that only multiple estimator based IFDIS schemes can have. Simulation results for various type of sensor faults show the detection and isolation performance of the IFDIS and the applicability of this scheme to fault tolerant control system design.

바이폴라 트랜지스터 소신호 변수의 결정 및 특성에 관한 연구 (Characterization and Determination of Small Signal Parameters of Bipolar Transistors)

  • 배동건;정상구;최연익;조영철
    • 대한전자공학회논문지
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    • 제27권1호
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    • pp.51-58
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    • 1990
  • NPN Si bipolar transistors with two different emitter widths are designed and fabricated. The effects of the emitter width on the small signal parameters of BJTs are measured and discussed. A new ac method for determining the current gain, the cut off frequency and the internal capacitances from the input impedance circle characteristics as a function of the varied external series resistances is presented. This method allows an accurate characterization of bipolar transistors with high current gain. The variation of the I-V curves of the emitter junction with the reverse collector junction voltages is discussed from the changes in the intsrinsic base resistances.

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외부 베이스표면을 에미터 ledge로 포장한 InGaP/GaAs HBT의 신뢰도 향상 (High Reliable GaAs HBT with InGaP Ledge Emitter Structure)

  • 박재홍;박재운
    • 한국컴퓨터정보학회논문지
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    • 제5권4호
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    • pp.102-105
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    • 2000
  • 외부 베이스 표면에 형성되는 표면 재결합 상태의 불안정성을 개선하기 위해 에미터 ledge 구조로 제작된 InGaP/GaAs HBT의 신뢰도 측정을 위해 고온에서 오랜 시간동안 정전류 스트레스를 인가하였다. 553K, 533K, 513K에서 콜렉터 전류 24㎃로 스트레스를 인가해 전류이득의 열화를 관찰하였다. 그 결과 EA=1.97eV, WTTF=4.8$\times$108시간(14$0^{\circ}C$)을 구하였다. InGaP/GaAs HBT의 열화 원인은 베이스 도펀트인 C의 확산으로 추정된다.

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Reactive Ion Etching Process Integration on Monocrystalline Silicon Solar Cell for Industrial Production

  • Yoo, Chang Youn;Meemongkolkiat, Vichai;Hong, Keunkee;Kim, Jisun;Lee, Eunjoo;Kim, Dong Seop
    • Current Photovoltaic Research
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    • 제5권4호
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    • pp.105-108
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    • 2017
  • The reactive ion etching (RIE) technology which enables nano-texturatization of surface is applied on monocrystalline silicon solar cell. The additional RIE process on alkalized textured surface further improves the blue response and short circuit current. Such parameter is characterized by surface reflectance and quantum efficiency measurement. By varying the RIE process time and matching the subsequent processes, the absolute efficiency gain of 0.13% is achieved. However, the result indicates potential efficiency gain could be higher due to process integration. The critical etch process time is discussed which minimizes both front surface reflectance and etching damage, considering the challenges of required system throughput in industry.

Design of Current-Type Readout Integrated Circuit for 160 × 120 Pixel Array Applications

  • Jung, Eun-Sik;Bae, Young-Seok;Sung, Man-Young
    • Journal of Electrical Engineering and Technology
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    • 제7권2호
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    • pp.221-224
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    • 2012
  • We propose a Readout Integrated Circuit (ROIC), which applies a fixed current bias sensing method to the input stage in order to simplify the circuit structure and the infrared sensor characteristic control. For the sample-and-hold stage to display and control a signal detected by the infrared sensor using a two-dimensional (2D) focal plane array, a differential delta sampling (DDS) circuit is proposed, which effectively removes the FPN. In addition, the output characteristic is improved to have wider bandwidth and higher gain by applying a two-stage variable gain amplifier (VGA). The output characteristic of the proposed device was 23.91 mV/$^{\circ}C$, and the linearity error rate was less than 0.22%. After checking the performance of the ROIC using HSPICE simulation, the chip was manufactured and measured using the SMIC 0.35 um standard CMOS process to confirm that the simulation results from the actual design are in good agreement with the measurement results.

단일 전류 센서를 이용하는 새로운 브리지 없는 인터리빙 방식의 역률 보상 회로 (A Novel Bridgeless Interleaved Power Factor Correction Circuit with Single Current Sensor)

  • 도안반투안;최우진
    • 전력전자학회:학술대회논문집
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    • 전력전자학회 2016년도 전력전자학술대회 논문집
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    • pp.363-364
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    • 2016
  • In this paper, a novel bridgeless interleaved power factor correction circuit with single current sensor is proposed. The proposed control strategy requires only one current sensor for the interleaved bridgeless PFC. By sampling the output current, all the boost indictor currents can be calculated and used to control the input current according to the input voltage. The reduced number of current sensors and associated feedback circuits helps reduce the cost of system. The problem caused by the unequal current gain between current sensors inherently does not exist in the proposed topology. Thus, current sharing between converters can be achieved more accurately and the high frequency distortion is decreased. In addition, the proposed technique can be applied to the other kinds of interleaved PFC topologies. Performance of the proposed control strategy is verified by the experimental results with 6.6kW bridgeless interleaved PFC circuit.

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A 6 Gb/s Low Power Transimpedance Amplifier with Inductor Peaking and Gain Control for 4-channel Passive Optical Network in 0.13 μm CMOS

  • Lee, Juri;Park, Hyung Gu;Kim, In Seong;Pu, YoungGun;Hwang, Keum Cheol;Yang, Youngoo;Lee, Kang-Yoon;Seo, Munkyo
    • JSTS:Journal of Semiconductor Technology and Science
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    • 제15권1호
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    • pp.122-130
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    • 2015
  • This paper presents a 6 Gb/s 4-channel arrayed transimpedance amplifiers (TIA) with the gain control for 4-channel passive optical network in $0.13{\mu}m$ complementary metal oxide semiconductor (CMOS) technology. A regulated cascode input stage and inductive-series peaking are proposed in order to increase the bandwidth. Also, a variable gain control is implemented to provide flexibility to the overall system. The TIA has a maximum $98.1dB{\Omega}$ gain and an input current noise level of about 37.8 pA/Hz. The die area of the fabricated TIA is $1.9mm{\times}2.2mm$ for 4-channel. The power dissipation is 47.64 mW/1ch.