• Proceedings of the IEEK Conference
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• summer
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• pp.218-220
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• 2004

A new wide-band VCO topology using Miller capacitance is proposed. Contrary to conventional VCO using the Miller capacitance where the variable amplifier gain is negative, the proposed VCO uses both the negative and positive variable amplifier gain to enhance the frequency tuning range significantly. The proposed VCO is simulated using HSPICE. The simulations show that 410MHz and 220MHz frequency tuning range are obtained using the negative .and positive variable amplifier gain, respectively. The tuning range of the proposed VCO is $23\%$ of the center frequency(2.8GHz). The phase noise is -104dBc/Hz at 1MHz offset by simple model. The operating current is only 3.84mA at 2.5V power supply.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.34C no.6
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• pp.37-43
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• 1997

In this paper, an analog-domain powr-reduction technique for a low-voltage CMOS operational amplifier and its application to clock-based VLSI systems are proposed. The proposed technique cuts off the bias current of the op amp during a half cycle of the clock in the sleeping mode and resumes the curent supply sequentially during the remaining cycle of the clock in the normal operating mode. The proposed sequential sbiasing technique reduces about 50% of the op amp power and improves the circuit performance through high phase margin and stable settling behavior of the output voltage. The power-reduction technique is applied to a sample-and-hold amplifier which is one of the critical circuit blocks used in the front-end stage of analog and/or digital integrated systems. The SHA was simulated and analyzed in a 0.8.mu.m n-well double-poly double-metal CMOS technology.

• Korean Journal of Optics and Photonics
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• v.2 no.2
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• pp.67-73
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• 1991

The unsaturated signal gain, signal gain bandwidth, and saturation power which are important parameters determining characteristics of the semiconductor laser amplifier were measured for an AlGaAs Fabry-Perot cavity type laser amplifier and compared with the results of Fabry-Perot formula. The unsaturated signal gain 25 dB is obtained near oscillation thereshold current at $0.7\mu\textrmW$ input power. The corresponding signal gain bandwidth was about 3 GHz. Also. We measured the variation of the saturation signal gain and saturation power.

• Proceedings of the KIEE Conference
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• 1994.11a
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• pp.141-143
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• 1994

The pulse width modulated class D power amplifier has the highest efficiency among various class amplifiers but the performances, such as bandwidth, distortion and stability are inferior to the conventional ones. In this paper, a new class D amplifier design is Presented employing dual feedback loops namely current and voltage feedback. The new design provides wide full-power bandwidth and stability at any load with high efficiency.

• Current Optics and Photonics
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• v.3 no.3
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• pp.236-242
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• 2019

An Nd:YAG slab structure was designed for a high-power zigzag slab laser amplifier based on computational simulation of the wavefront distortion. For the simulation, the temperature distribution in the slab was calculated at first by thermal analysis. Then, the optical path length (OPL) was obtained by a ray tracing method for the corresponding refractive index variation inside the slab. After that, the OPL distribution of the double-pass amplified beam was calculated by summing the results obtained for the first and second passes. The amount of wavefront distortion was finally obtained as the peak-to-valley value of the OPL distribution. As a result of this study, the length and position of the gain medium were optimized by minimizing the transverse wavefront distortion. Under the optimized conditions, the transverse wavefront distortion of the double-pass amplified beam was less than $0.2{\mu}m$ for pump power of 14 kW.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.41 no.9
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• pp.25-30
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• 2004

In this Paper, the 0.1 w InGaAs/InAlAs/GaAs Metamorphic HEMT, which is applicable to MIMIC, and a 100 GHz MIMIC amplifier were designed and fabricated. The DC characteristics of MHEMT are 640 mA/mm of drain current density, 653 mS/mm of maximum transconductance. The current gain cut-off frequency(fT) is 173 GHz and the maximum oscillation frequency(fmax) is 271 GHz. A 100 GHz amplifier was designed using 0.1${\mu}{\textrm}{m}$ MHEMT and CPW technology. The measured results from the 100 GHz MIMIC amplifiers show good S21 gain of 10.1 dB and 12.74 dB at 100 GHz and 97.8 GHz, respectively.

• Journal of the Institute of Electronics and Information Engineers
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• v.53 no.9
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• pp.62-66
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• 2016

This paper presents a MedRadio-band low power low noise amplifier for Medical Devices. A proposed MedRadio-band low power low noise amplifier adopts a current-reuse resistive feedback topology to increase overall gm and reduce power consumption. The gain of the LNA increases by the Q-factor of the additional series RLC input matching network, and its noise figure is minimized by the similar factor. Furthermore, it consumes low power because of low supply voltage and current reuse technique. By exploiting the $g_m$-booting and matching network property, the proposed MedRadio-band low noise amplifier achieves a noise figure of 0.85 dB, a voltage gain of 30 dB, and IIP3 of -7.9 dBm while consuming 0.18 mA from a 1 V supply voltage in $0.13{\mu}m$ CMOS technology.

• Journal of electromagnetic engineering and science
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• v.14 no.4
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• pp.393-398
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• 2014

A highly efficient dual-mode linear CMOS stacked-FET power amplifier (PA) is implemented for 3G UMTS and 4G LTE handset applications. High efficiency is achieved at a backed-off output power ($P_{out}$) below 12 dBm by employing an active-bypass amplifier, which consumes very low quiescent current and has high load-impedance. The output paths between high- and low-power modes of the PA are effectively isolated by using a bypass switch, thus no RF performance degradation occurs at high-power mode operation. The fabricated 900 MHz CMOS PA using a silicon-on-insulator (SOI) CMOS process operates with an idle current of 5.5 mA and shows power-added efficiency (PAE) of 20.5%/43.5% at $P_{out}$ = 12.4 / 28.2 dBm while maintaining an adjacent channel leakage ratio (ACLR) better than -39 dBc, using the 3GPP uplink W-CDMA signal. The PA also exhibits PAE of 35.1% and $ACLR_{E-UTRA}$ of -33 dBc at $P_{out}$ = 26.5 dBm, using the 20 MHz bandwidth 16-QAM LTE signal.

• Journal of electromagnetic engineering and science
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• v.14 no.3
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• pp.284-292
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• 2014

This paper presents a characteristic evaluation of commercial gallium nitride (GaN) transistors having two different gate-lengths of $0.4-{\mu}m$ and $0.25-{\mu}m$ in the design of a class-S power amplifier (PA). Class-S PA is operated by a random pulse-width input signal from band-pass delta-sigma modulation and has to deal with harmonics that consider quantization noise. Although a transistor having a short gate-length has an advantage of efficient operation at higher frequency for harmonics of the pulse signal, several problems can arise, such as the cost and export license of a $0.25-{\mu}m$ transistor. The possibility of using a $0.4-{\mu}m$ transistor on a class-S PA at 955 MHz is evaluated by comparing the frequency characteristics of GaN transistors having two different gate-lengths and extracting the intrinsic parameters as a shape of the simplified switch-based model. In addition, the effectiveness of the switch model is evaluated by currentmode class-D (CMCD) simulation. Finally, device characteristics are compared in terms of current-mode class-S PA. The analyses of the CMCD PA reveal that although the efficiency of $0.4-{\mu}m$ transistor decreases more as the operating frequency increases from 955 MHz to 3,500 MHz due to the efficiency limitation at the higher frequency region, it shows similar power and efficiency of 41.6 dBm and 49%, respectively, at 955 MHz when compared to the $0.25-{\mu}m$ transistor.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.17 no.1
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• pp.158-165
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• 2013

In this paper, a new circuit topology of an ultra-wideband (UWB) 3.1-10.6GHz CMOS low noise amplifier is presented. The proposed UWB low noise amplifier is designed utilizing RC feedback and LC filter networks which can provide good input impedance matching. In this design, the current-reused topology is adopted to reduce the power consumption and the inductor-peaking technique is applied for the purpose of bandwidth extension. The performance results of this UWB low noise amplifier simulated in $0.18-{\mu}m$ CMOS process technology exhibit a power gain of 14-14.9dB, an input matching of better than -10.8dB, gain flatness of 0.9dB, and a noise figure of 2.7-3.3dB in the frequency range of 3.1-10.6GHz. In addition, the input IP3 is -5dBm and the power consumption is 12.5mW.