• Proceedings of the IEEK Conference
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• 2004.08c
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• pp.494-498
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• 2004

In this paper, the design of a CMOS exponential V-I converter (EVIC,) based on Taylor's concept, is presented. The composite NMOS transistor is used for realizing the exponential characteristics. In a 0.25 $\mu$m CMOS process, the simulations show more than 20 dB output current range and 15 dB linear range with the linearity error less than $\pm$ 0.5 dB. The power dissipation is less than 0.3 mW with $\pm$ 1.5 V supply voltage. The proposed EVIC can be used for the design of an extremely low­voltage and low-power variable gain amplifier (VGA) and automatic gain control (AGC).

• Proceedings of the KIEE Conference
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• 1991.11a
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• pp.231-233
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• 1991

This paper discribes a study on the switching character of MOS-GTO and the design of gate drive circuit. Chopping power supply converter, synchronious and asyncronious motor speed adjustment, inverter, etc., needs low drive energy "high frequency" switches. To fulfill these need, switches must have rapid switching time and insulated gate control. MOS-GTO structure is well suited to these constraints. The power switch is serial installation of a GTO thyrister and a MOS Transistor. The gate of the GTO is linked to positive pole of the cascode structure via a MOS high voltage transistor and ground via a transient absorber diode. This high performance MOS-GTO assembly considerably increases the strength which facilitate the drive of GTO thyristers.

• Journal of the Korean Institute of Telematics and Electronics
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• v.10 no.6
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• pp.11-24
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• 1973

A new simple technique for 2-terminal negative resistance cireait analysis and synthesis is developed, by using the equivalent e.m.f. defined as a function of input lotage or current variation. The technique is applied to design 2-terminal junction transistor negative resistance circuits based on the parameter control method. Modeling circuits for SCR, GTO-SCR and SSS are also derived from the proposed transistor negative resistance circuits, and the merits of the modeling circuits are discussed.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2002.07b
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• pp.1063-1066
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• 2002

An equivalent circuit for the superconductor flux flow transistor(SFFT) was combined with high temperature cooling device, based on the analogy between thermal and electrical variables using the high-temperature superconductor(HTS), is proposed. The device is composed of parallel weak links with a nearby magnetic control line. A model has been developed that is based on solving the equation of motion of Abrikosov vortices subject to Lorentz viscous and pinning forces as well as magnetic surface barriers. The use of thermal models the global performance of thermal cooling circuit and signal system to be checked by using electrical circuit analysis programs such as SPICE.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2010.03b
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• pp.40-40
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• 2010

CdSe nanocrystals (NCs) have been decorated on singlewalled carbon nanotubes (SWCNTs) by combining a method of chemically modified substrate along with gate-bias control. CdSe/ZnS core/shell quantum dots were negatively charged by adding mercaptoacetic acid (MAA). The silicon oxide substrate was decorated by octadecyltrichlorosilane (OTS) and converted to hydrophobic surface. The negatively charged CdSe NCs were adsorbed on the SWCNT surface by applying the negative gate bias. The selective adsorption of CdSe quantum dots on SWCNTs was confirmed by confocal laser scanning microscope. The measured photocurrent clearly demonstrates that CdSe NCs decorated SWCNT can be used for photodetector and solar cell that are operable over a wide range of wavelengths.

• JSTS:Journal of Semiconductor Technology and Science
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• v.8 no.1
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• pp.51-65
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• 2008

The article presents the recent research development in polymer ferroelectric non-volatile memory. A brief overview is given of the history of ferroelectric memory and device architectures based on inorganic ferroelectric materials. Particular emphasis is made on device elements such as metal/ferroelectric/metal type capacitor, metal-ferroelectric-insulator-semiconductor (MFIS) and ferroelectric field effect transistor (FeFET) with ferroelectric poly(vinylidene fluoride) (PVDF) and its copolymers with trifluoroethylene (TrFE). In addition, various material and process issues for realization of polymer ferroelectric non-volatile memory are discussed, including the control of crystal polymorphs, film thickness, crystallization and crystal orientation and the unconventional patterning techniques.

• JSTS:Journal of Semiconductor Technology and Science
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• v.13 no.4
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• pp.361-366
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• 2013

A full-range analytic drain current model for depletion-mode long-channel surrounding-gate nanowire field-effect transistor (SGNWFET) is proposed. The model is derived from the solution of the 1-D cylindrical Poisson equation which includes dopant and mobile charges, by using the Pao-Sah gradual channel approximation and the full-depletion approximation. The proposed model captures the phenomenon of the bulk conduction mechanism in all regions of device operation (subthreshold, linear, and saturation regions). It has been shown that the continuous model is in complete agreement with the numerical simulations.

• JSTS:Journal of Semiconductor Technology and Science
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• v.13 no.5
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• pp.530-537
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• 2013

An explicit surface potential calculation method of gate-all-around MOSFET (GAAMOSFET) devices which takes into account both interface trap charge and varying doping levels is presented. The results of the method are extensively verified by numerical simulation. Results from the model are used to find qualitative and quantitative effect of interface trap charge on subthreshold slope (SS) of GAAMOSFET devices. Further, design constraints of GAAMOSFET devices with emphasis on the effect of interface trap charge on device SS performance are investigated.

• Korean Journal of Materials Research
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• v.17 no.4
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• pp.232-235
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• 2007

Indium tin oxide (ITO) films were deposited on polycarbonate CR39 substrate using DC magnetron sputtering. ITO thin films were deposited at room temperature because glass-transition temperature of CR39 substrate is $130^{circ}C$ ITO thin films are used as bottom and top electrodes and for organic thin film transparent transistor (OTFT). The electrodes electrical properties of ITO thin films and their optical transparency properties in the visible wavelength range (300-800 nm) strongly depend on the volume of oxygen percent. The optimum resistivity and transparency of ITO thin film electrode was achieved with a 75 W plasma power, 10 % volume of oxygen and a 27 nm/min deposition rate. Above 85% transparency in the visible wavelength range (300-800 nm) was measured without post annealing process, and resistivity as low as $9.83{\times}^{TM}10^{-4}{\Omega}$ cm was measured at thickness of 300 nm.

• JSTS:Journal of Semiconductor Technology and Science
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• v.14 no.4
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• pp.451-456
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• 2014

A compact model of a depletion-mode silicon-nanowire (Si-NW) pH sensor is proposed. This drain current model is obtained from the Pao-Sah integral and the continuous charge-based model, which is derived by applying the parabolic potential approximation to the Poisson's equation in the cylindrical coordinate system. The threshold-voltage shift in the drain-current model is obtained by solving the nonlinear Poisson-Boltzmann equation for the electrolyte. The simulation results obtained from the proposed drain-current model for the Si-NW field-effect transistor (SiNWFET) agree well with those of the three-dimensional (3D) device simulation, and those from the Si-NW pH sensor model also agree with the experimental data.