• Journal of the Institute of Electronics Engineers of Korea TC
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• v.47 no.10
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• pp.74-79
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• 2010

In this paper, a high gain W-band amplifier is presented using 70 run mHEMT MMIC technology. The length of source feedback line of common-source FET is carefully determined to maximize the gain at a design frequency. Simulation shows that MAG can be increased by 0.8 dB by optimizing the length of this line. In addition, this feedback line changes the input impedance of the common-source FET in a way that the input match can be made easier. In this work, 4-stage amplifier is designed on CPW using the source feedback. The measurement shows the excellent gain performance higher than 22.0 dB across 70~103 GHz.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.44 no.7 s.361
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• pp.41-46
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• 2007

A novel post-linearization technique is proposed for CMOS cascode low noise amplifier (LNA). The technique uses dual common gate FETs one of which delivers the linear currents to a load and the other one sinks the $3^{rd}$ order intermodulation currents of output currents from the common source FET. Selective current branching can be implemented in $0.18{\mu}m$ CMOS process by using a thick oxide FET as an IM3 sinker with a normal FET as a linear current buffer. A differential LNA adopting this technique is designed at 2.14GHz. The measurement results show 11dBm IIP3, 15.5dB power gain and 2.85dB noise figure consuming 12.4mA from 1.8V power supply. Compared with the LNA with turning off the IM3 sinker, the proposed technique improves the IIP3 by 7.5 dB.

• Proceedings of the KAIS Fall Conference
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• 2001.05a
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• pp.135-138
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• 2001

본 논문에서는 교류 전원인 220V 전원을 간단한 다이오드 및 커패시터만으로 정류한 후 BLDC 모터를 구동할 수 있는 드라이버를 개발하였다. 구동단은 저렴한 전력용 트랜지스터와 FET를 사용함으로써 비용을 줄일 수 있게 하였으며, 실험 결과 잘 동작함을 확인하였다.

• Journal of electromagnetic engineering and science
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• v.14 no.2
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• pp.68-73
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• 2014

A linear stacked field-effect transistor (FET) power amplifier (PA) is implemented using a $0.18-{\mu}m$ silicon-on-insulator CMOS process for W-CDMA handset applications. Phase distortion by the nonlinear gate-source capacitance ($C_{gs}$) of the common-source transistor, which is one of the major nonlinear sources for intermodulation distortion, is compensated by employing a PMOS linearizer with improved AM-PM. The linearizer is used at the gate of the driver-stage instead of main-stage transistor, thereby avoiding excessive capacitance loading while compensating the AM-PM distortions of both stages. The fabricated 836.5 MHz linear PA module shows an adjacent channel leakage ratio better than -40 dBc up to the rated linear output power of 27.1 dBm, and power-added efficiency of 45.6% at 27.1 dBm without digital pre-distortion.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.15 no.2
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• pp.140-144
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• 2004

The selectable dual band LNA usually uses common source transistor pair each input of which is selectively driven at a different frequency in a series resonant form. This paper analyzes the degradation in noise figures of the MOSFET common source pair with series resonance when it is driven concurrently at both inputs with different frequencies as a concurrent dual band LNA. Results of analysis will be compared with the measured noise figures of CMOS LNA with double inputs fabricated in 0.18 $\mu\textrm{m}$ CMOS process. Additionally, analyzing the contributions of FET channel noise and source noise from the LNA operating in the other band, this paper proposes optimum matching topology which minimizes the added noises for concurrent operation.

• Journal of the Institute of Electronics and Information Engineers
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• v.52 no.10
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• pp.33-46
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• 2015

In this paper, we predicts the analog and digital circuit performance of FinFETs that are scaled down following the ITRS(International technology roadmap for semiconductors). For accurate prediction of the circuit performance of scaled down devices, accurate parasitic resistance and capacitance analytical models are developed and their accuracies are within 2 % compared to 3D TCAD simulation results. The parasitic capacitance models are developed using conformal mapping, and the parasitic resistance models are enhanced to include the fin extension length($L_{ext}$) with respect to the default parasitic resistance model of BSIM-CMG. A new algorithm is developed to fit the DC characteristics of BSIM-CMG to the reference DC data. The proposed capacitance and resistance models are implemented inside BSIM-CMG to replace the default parasitic model, and SPICE simulations are performed to predict circuit performances such as $f_T$, $f_{MAX}$, ring oscillators and common source amplifier. Using the proposed parasitic capacitance and resistance model, the device and circuit performances are quantitatively predicted down to 5 nm FinFET transistors. As the FinFET technology scales, due to the improvement in both DC characteristics and the parasitic elements, the circuit performance will improve.

• Proceedings of the IEEK Conference
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• 2005.11a
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• pp.261-264
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• 2005

This paper presents the design of a down-conversion mixer with built-in active balun integrated in a $0.25\;{\mu}m$ pHEMT process. The active balun consists of series-connected common-gate FET and common-source FET. The designed balun achieved broadband characteristics by optimizing gate-width and bias condition for the reduction in parasitic effect. From DC to more than 6GHz, the active balun shows the phase error of less than 3 degree and the gain error of less than 0.4 dB. A single-balanced down-conversion mixer with built-in broadband active balun has been designed with optimum width, load resistor and bias for conversion gain and without any matching component for broadband operating. The designed mixer whose size of including on-chip bias circuit is $1\;mm{\times}1\;mm$ shows the conversion gain of better than 7 dB from 2 GHz to 6 GHz and $P_{1dB}$ of -10 dBm at 5.8 GHz

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.24 no.3
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• pp.278-285
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• 2013

In this paper, a 100~110 GHz LNA and A coupler using standard 65 n CMOS process is presented. The LNA consists of three common source FET stages. A few layout types are considered to get high gain characteristic of unit common source cell. Also, optimized performance to achieve low noise characteristic and enough gain. Coupler is composed of broadside coupler using multimetal in CMOS fabrication. In the coupler, the metal strip to meet density rule is used, and the coupler is designed with consideration of the metal strip to function properly. Gain of fabricated LNA is 5.64 dB at 100 GHz and 6.39 dB at 110 GHz. Bandwidth is over 10 % and noise figure is 11.66 dB at 100 GHz. Fabricated coupler has shown insertion loss of 2~3 dB at 100~110 GHz band. Magnitude mismatch of coupler is below 1 dB and phase mismatch of coupler is below $5^{\circ}$.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.29 no.6A
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• pp.697-704
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• 2004

This paper describes the design and fabrication of an MMIC variable gain LNA for 5GHz wireless LAN applications, using 0.5${\mu}{\textrm}{m}$ gate length GaAs MESFET transistors. The advantages of high gain and low noise performance of E-MESFETS and excellent linear performance of D-MESFETS are combined as a cascode topology in this design. Behavioral model equations are derived from the MESFET nonlinear current voltage characteristics by using Turlington's asymptote method in a cascode configuration. Using the behavioral model equations, a 4${\times}$50${\mu}{\textrm}{m}$ E-MESFET as a common source amplifier and a 2${\times}$50${\mu}{\textrm}{m}$ D-MESFET as a common gate amplifier are determined for the cascode amplifier. The fabricated variable gain LNA shows a noise figure of 2.4dB, variable gain range of more than 17dB, IIP3 of -4.8dBm at 4.9GHz, and power consumption of 12.8mW.

• Journal of the Korean Institute of Telematics and Electronics D
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• v.34D no.10
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• pp.14-23
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• 1997

An MMIC downconverting mixer for cellular phone application has been successfully developed using an MMIC process including $1 \mu\textrm{m}$ ion implanted gaAs MESFET and passive lumped elements consisting of spiral inductor, $Si_3N_4$ MIM capacitor and NiCr resistor. The configuration of the mixer presented in this paper is single-ended dual-gate FET mixer with common-source self-bias circuits for single power supply operation. The dimension of the fabricated circuit is $1.4 mm \times 1.03 mm $ including all input matching circuits and a mixing circuit. The conversion gian and noise figure of the mixer at LO powr of 0 dBm are 5.5dB and 19dB, respectively. The two-tone IM3 characteristics are also measured, showing -60dBc at RF power of -30dBm. Allisolations between each port show better than 20dB.