• 한국전자통신학회논문지
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• 제9권7호
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• pp.761-766
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• 2014

본 연구는 1 V 미만 전원 전압에서 동작 가능한 직렬공진 바렉터 통합형 평형 공통 게이트 콜피츠 전압제어 발진기와 직렬공진 바렉터 통합형 평형 공통 드레인 콜피츠 전압제어 발진기의 탱크회로에서 나타나는 발진전압에 대한 해석적 연구를 수행하고 이를 시뮬레이션에 의해 확인한다. 해석적 연구의 결과는 직렬공진 바렉터 통합형 평형 공통 게이트 콜피츠 전압제어 발진기가 직렬공진 바렉터 통합형 평형 공통 드레인 콜피츠 전압제어 발진기보다 더 큰 발진전압을 탱크회로에 유도할 수 있으며 따라서 저 위상 잡음 발진에 보다 더 적합한 발진기임을 밝혀준다.

• 산업경영시스템학회지
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• 제32권4호
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• pp.128-133
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• 2009

Brain drain of scientists and technologists to the United States from other countries is a phenomenal issue due to the potential developmental impacts it could have on sending countries. Immigration policies undoubtedly play the major part to shape the human resource outcomes. There has been a common sense explanation to the brain drain trend, which states that the lower English language requirements in the scientific and technology jobs compared to other high skill brain drain jobs offer immigrants more favorable employment opportunities. These and other language related variables are used with standard human capital model variables to assess the validity of the common sense proposition.

• Transactions on Electrical and Electronic Materials
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• 제7권4호
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• pp.180-183
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• 2006

We report for the first time two-bit operational characteristics of a high-density NOR-type polysilicon-oxide-nitride-oxide-silicon (SONOS) array with common source line (CSL). An undesired disturbance, especially drain disturbance, in the NOR array with CSL comes from the two-bit-per-cell operation. To solve this problem, we propose an efficient bulk-biased programming technique. In this technique, a bulk bias is additionally applied to the substrate of memory cell for decreasing the electric field between nitride layer and drain region. The proposed programming technique shows free of drain disturbance characteristics. As a result, we have accomplished reliable two-bit SONOS array by employing the proposed programming technique.

• Journal of Chest Surgery
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• 제46권3호
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• pp.223-225
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• 2013

Chest draining is a common procedure for treating pleural effusion. Perforation of the heart is a rare often fatal complication of chest drain insertion. We report a case of a 76-year-old female patient suffering from congestive heart failure. At presentation, unilateral opacity of the left chest observed on a chest X-ray was interpreted as massive pleural effusion, so an attempt was made to drain the left pleural space. Malposition of the chest drain was suspected because blood was draining in a pulsatile way from the catheter. Computed tomography revealed perforation of the left ventricle. Mini-thoracotomy was performed and the drain extracted successfully.

• 전기의세계
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• 제30권10호
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• pp.645-654
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• 1981

A technique has been proposed for fabricating a submicron channel vertical V-groove JFET using standard photolithography. A finite element numerical simulation of the V-groove JFET operation was performed using a FORTRAN progrma run on a Cyber-174 computer. The numerical simulation predicts pentode like common source output characteristics for the p$^{+}$n Vertical V-groove JFET with maximum transconductance representing approximately 6 precent of the zero bias drain conductance value and markedly high drain conductance at large drain voltages. An increase in the acceptor concentration of the V-groove JFET gate was observed to cause a significant increase in the transconductance of the device. Therefore, as above mentioned, this paper is study on the analysis of a Vertical V-groove Junction Field Effect Transistor with Finite Element Method.d.

• 한국전자파학회논문지
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• 제20권9호
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• pp.900-905
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• 2009

본 논문에서는 전류 블리딩(bleeding)과 입력 인덕티브 직렬-피킹을 이용한 공통 드레인 귀환(Common Drain Feedback: CDFB) CMOS 광대역 저잡음 증폭기(Low Noise Amplifier: LNA)를 설계하였다. 캐스코드 증폭기와 귀환 증폭기를 DC 결합하여 블리딩 전류의 조정을 통해 LNA의 이득과 잡음 지수(Noise figure: NF)의 동적 제어를 실현하였다. 제작한 LNA는 2.5 GHz의 대역폭에서, 고이득 영역은 $1.7{\sim}2.8\;dB$ NF와 17.5 dB 이득, 그리고 27 mW의 전력 소비를 보이고, 저 이득 영역은 $2.7{\sim}4.0\;dB$ NF와 14 dB 이득, 그리고 1.8 mW의 전력 소비를 보인다.

• 스마트미디어저널
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• 제4권2호
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• pp.55-61
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• 2015

A bandwidth-enhanced ultra-wide band (UWB) CMOS balun-LNA is implemented as a part of a software defined radio (SDR) receiver which supports multi-band and multi-standard. The proposed balun-LNA is composed of a single-to-differential converter, a differential-to-single voltage summer with inductive shunt peaking, a negative feedback network, and a differential output buffer with composite common-drain (CD) and common-source (CS) amplifiers. By feeding the single-ended output of the voltage summer to the input of the LNA through a feedback network, a wideband balun-LNA exploiting negative feedback is implemented. By adopting a source follower-based inductive shunt peaking, the proposed balun-LNA achieves a wider gain bandwidth. Two LNA design examples are presented to demonstrate the usefulness of the proposed approach. The LNA I adopts the CS amplifier with a common gate common source (CGCS) balun load as the S-to-D converter for high gain and low noise figure (NF) and the LNA II uses the differential amplifier with the ac-grounded second input terminal as the S-to-D converter for high second-order input-referred intercept point (IIP2). The 3 dB gain bandwidth of the proposed balun-LNA (LNA I) is above 5 GHz and the NF is below 4 dB from 100 MHz to 5 GHz. An average power gain of 18 dB and an IIP3 of -8 ~ -2 dBm are obtained. In simulation, IIP2 of the LNA II is at least 5 dB higher than that of the LNA I with same power consumption.

• 전력전자학회:학술대회논문집
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• 전력전자학회 2001년도 Proceedings ICPE 01 2001 International Conference on Power Electronics
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• pp.212-216
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• 2001

Because conventional switching converters have been usually using unbalanced circuit topologies, parasitic capacitance between the drain/collector of an active switch and the frame ground through its heat sink may generate the common-mode conducted noise. We have proposed a balanced switching converter circuit, which is an effective way to reduce the common-mode conducted noise. As an example, a boost converter version of the balanced switching converter was presented and the mechanism of the common-mode noise reduction was explained using equivalent circuits. This paper extends the concept of the balanced switching converter circuit and presents a buck-boost converter version of the balanced switching converter. The feature of common-mode noise reduction is confirmed by experimental results and the mechanism of the common-mode noise reduction is explained using equivalent circuits.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2000년도 하계종합학술대회 논문집(2)
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• pp.133-136
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• 2000

A new Op-Amp output buffer is presented for driving large-size LCD panels. The proposed Op-Amp is designed by combining a common source and a common drain amplifier to have a high slew rate and to minimize the quiescent current. The proposed circuits are simulated in a high-voltage 0.6${\mu}{\textrm}{m}$ CMOS process, dissipates only 20${\mu}{\textrm}{m}$ static current, and have 83dB open-loop DC gain and 60$^{\circ}$phase margin.

• 전자공학회논문지SC
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• 제39권4호
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• pp.25-35
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• 2002

본 논문에서는 단일 폴리 공정을 기반으로 하여 8b 해상도로 200MHz의 고속 동작을 하기 위해 최적화된 시간 공유 서브레인징 ADC(Analog-to-Digital Converter)를 제안한다. 제안하는 ADC는 높은 정확도를 요구하는 하위 ADC에 이중 채널 구조를 적용하여 높은 샘플링 주파수를 보장하였고, 새로운 기준 전압 인가 방식을 적용하여 기준 전압의 빠른 정착 시간을 얻으면서 동시에 칩 면적을 크게 감소시켰다. 기준 전압을 생성하는 저항열에서는 선형성 및 속도 향상을 위해 기존의 인터메쉬드 구조를 보완한 새로운 저항열을 사용하였다. 8 비트 수준의 정밀도에서 면적 및 전력 소모를 최소화하기 위해 공통 드레인(common- drain) 증폭기 구조를 사용하여 샘플-앤-홀드 증폭기(Sample-and-Hold Amplifier：SHA)를 설계하였으며, 입력단에 스위치와 캐패시터로 구성된 동적 공통 모드 궤환 회로(Dynamic Common Mode Feedback Circuit)를 사용하여 SHA의 동적 동작 범위(dynamic range)를 증가시켰다. 동시에 상위 ADC와 하위 ADC간의 신호 처리를 단순화시키기 위해 상위 ADC에 새로운 인코딩 회로를 제안하였다.